Abstract
Reducing the power consumption of AES circuits is a critical problem when the circuits are used in low power embedded systems. We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of dynamic hazards. In this paper, we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields. In this S-Box, (i) the signal arrival times of gates are as close as possible if the depths of the gates from the primary inputs are the same, and (ii) the hazard-transparent XOR gates are located after the other gates that may block the hazards. A low power consumption of 29 μW at 10 MHz using 0.13 μm 1.5V CMOS technology was achieved, while the consumptions of the BDD, SOP, and composite field S-Boxes are 275, 95, and 136 μW, respectively.
Chapter PDF
Similar content being viewed by others
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
J. Daemen and V. Rijmen, “AES Proposal: Rijndael,” http://csrc.nist.gov/ encryption/aes/rijndael/Rijndael.pdf.
National Institute of Standards and Technology (NIST), “Advanced Encryption Standard (AES)”, FIPS Publication 197, http://csrc.nist.gov/encryption/ aes/index.html, Nov. 2001.
H. Kuo et al., “Architectural Optimization for a 1.82 Gbits/sec VLSI Implementation of the AES Rijndael Algorithm,” Proc. CHES2001, LNCS Vol. 2162, pp. 53–67, 2001.
B. Weeks et al., “Hardware Performance Simulation of Round 2 Advanced Encryption Standard Algorithm,” http://csrc.nist.gov/encryption/aes/round2/ NSA-AESfinalreport.pdf.
M. McLoone et al., “High performance single-chip FPGA Rijndael algorithm implementations,” Proc. CHES2001, LNCS Vol. 2162, pp. 68–80, 2001.
V. Fischer et al, “Two methods of Rijndael implementation in reconfigurable hardware,” Proc. CHES2001, LNCS Vol. 2162, pp. 81–96, 2001.
A.P. Chandrakasan and R.W. Brodersen (eds.), Low Power Digital CMOS Design, Kluwer Academic Publishers, 1995.
J. Guajardo and C. Paar, “Efficient Algorithms for Elliptic Curve Cryptosystems,” CRYPTO’97, LNCS Vol. 1294, pp. 342–356, 1997.
A. Rudra et al, “Efficient Rijndael encryption implementation with composite field arithmetic,” Proc. CHES2001, LNCS Vol. 2162, pp. 175–188, 2001.
A. Satoh, S. Morioka, K. Takano, and S. Munetoh, “A Compact Rijndael Hardware Architecture with S-Box Optimization,” Advances in Cryptology-ASIACRYPT 2001, LNCS Vol. 2248, pp. 239–254, 2001.
T. Sasao, “AND-EXOR expressions and their optimization”, in Sasao, editor: Logic Synthesis and Optimization, Kluwer Academic Publishers, pp. 287–312, 1993.
I.F. Blake, X. Gao, R.C. Mullin, S.A. Vanstone and T. Yaghoobian, Applications of Finite Fields, Kluwer Academic Publishers. 1993.
T. Itoh and S. Tsujii, “A Fast Algorithm for Computing Multiplicative Inverses in GF(2m) using Normal Bases,” Information and Computation, Vol.78, No. 3, pp. 171–177, 1988.
S. Morioka and Y. Katayama, “O(log2m) Iterative Algorithm for Multiplicative Inverse in GF(2m),” IEEE Intl. Symp. On Info. Theory (ISIT2000), pp. 449 ff., 2000.
R.E. Bryant, “Graph-Based Algorithms for Boolean Function Manipulation,” IEEE Trans. on Computers, Vol. C-35, No. 8, pp. 677–691, 1986.
S. Morioka, Y. Katayama, and T. Yamane, “Towards Efficient Verification of Arithmetic Algorithms over Galois Fields GF(2m),” 13th Conference on Computer Aided Verification (CAV’01), LNCS Vol. 2102, pp. 465–477, 2001.
S. Morioka and A. Satoh, “A 10 Gbps Full-AES Crypto Design with a Twisted-BDD SBox Architecture,” 2002 IEEE Intl. Conf. on Computer Design (ICCD2002), 2002.
S. Morioka and Y. Katayama, “Design Methodology for one-shot Reed-Solomon Encoder and Decoder,” 1999 IEEE Intl. Conf. on Computer Design (ICCD’99), pp. 60–67, 1999.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Morioka, S., Satoh, A. (2003). An Optimized S-Box Circuit Architecture for Low Power AES Design. In: Kaliski, B.S., Koç, ç.K., Paar, C. (eds) Cryptographic Hardware and Embedded Systems - CHES 2002. CHES 2002. Lecture Notes in Computer Science, vol 2523. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36400-5_14
Download citation
DOI: https://doi.org/10.1007/3-540-36400-5_14
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-00409-7
Online ISBN: 978-3-540-36400-9
eBook Packages: Springer Book Archive