Abstract
In this paper we propose a novel scheduling framework for a dynamic real-time environment that experiences power consumption constraints. This framework is capable of dynamically adjusting the voltage/speed of the system, such that no task in the system misses its deadline and the total energy savings of the system are maximized.
Each task in the system consumes a certain amount of energy, which depends on a speed chosen for execution. The process of selecting speeds for execution while maximizing the energy savings of the system requires the exploration of a large number of combinations, which is too time consuming to be computed on-line. Thus, we propose an integrated heuristic methodology which executes an optimization procedure and an approximate greedy algorithm in a low computation time. This scheme allows the scheduler to handle power-aware real-time tasks with low cost while maximizing the use of the available resources and without jeopardizing the temporal constraints of the system. Simulation results show that our heuristic methodology achieves a performance with near-optimal results.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
H. Aydin, R. Melhem, D. Mosse, P. Mejia. “Determining Optimal Processor Speeds for Periodic Real-Time Tasks with Different Power Characteristics”. EuroMicro Conference on Real-Time Systems, June 2001.
H. Aydin, R. Melhem, D. Mosse, P. Mejia. “Dynamic and Aggressive Scheduling Techniques for Power-Aware Real-Time Systems”. IEEE Real-Time Systems Symposium, Dec. 2001.
T. D. Burd, T. A. Pering, A. J. Stratakos, R. W. Brodersen, “A Dynamic Voltage Scaled Microprocessor System”, IEEE J. of Solid-State Circuits, Vol. 35, No. 11, Nov. 2000.
F. Gruian, K. Kuchcinski. “LEneS:Task Scheduling for Low Energy Systems Using Variable Supply Voltage Processors”. In Proc. Asia South Pacific-DAC Conference 2001, June 2001.
I. Hong, D. Kirovski, G. Qu, M. Potkonjak and M. Srivastava. “Power Optimization of Variable Voltage Core-Based Systems”. In Design Automation Conference, 1998.
I. Hong, M. Potkonjak and M. B. Srivastava. “On-line Scheduling of Hard Real-Time Tasks on Variable Voltage Processor”. In Computer-Aided Design (IC-CAD)’98, 1998.
I. Hong, G. Qu, M. Potkonjak and M. Srivastava. “Synthesis Techniques for Low-Power Hard Real-Time Systems on Variable Voltage Processors”. In Proc. of 19th IEEE Real-Time Systems Symposium, Madrid, December 1998.
Intel, Microsoft, Compaq, Phoenix and Toshiba. “ACPI Specification”, http://developer.intel.com/technology/IAPC/tech.
Intel StrongARM SA-1100 microprocessor developer’s manual.
T. Ishihara and H. Yasuura. “Voltage Scheduling Problem for Dynamically Varying Voltage Processors”, In Proc. Int’ l Symposium on Low Power Electronics and Design, 1998.
C. M. Krishna and Y. H. Lee. “Voltage Clock Scaling Adaptive Scheduling Techniques for Low Power in Hard Real-Time Systems”. In Proc. of the IEEE Real-Time Technology and Applications Symposium, 2000.
E. Lawler. “Fast Approximation Algorithms for Knapsack Problems”. Mathematics of Operations Research, Nov. 1979.
C. L. Liu, J. Layland. “Scheduling Algorithms for Multiprogramming in Hard Real-Time Environments”, J. ACM, 20(1). Jan. 1973.
G. Lipari, G. Buttazzo. “Schedulability Analysis of Periodic and Aperiodic Tasks with Resource Constraints”, J. of Systems Architecture, (46). 2000.
J. R. Lorch, A. J. Smith. “Improving Dynamic Voltage Scaling Algorithms with PACE”. In Proc. of ACM SIGMETRICS Conference Cambridge, MA, June 2001.
S. Martello and P. Toth. “Knapsack Problems. Algorithms and Computer Implementations”. Wiley, 1990.
D. Mosse, H. Aydin, B. Childers, R. Melhem. “Compiler Assisted Dynamic Power-Aware Scheduling for Real-Time Applications”. In Workshop on Compiler and Operating Systems for Low Power COLP’00 October, 2000.
D. Pisinger. “A Minimal Algorithm for the Multiple-Choice Knapsack Problem”, European Journal of Operational Research, 83. 1995.
Y. Shin and K. Choi. “Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems”. In Proc. of the Design Automation Conference. 1999.
P. Sinha, A. Zoltners. “The Multiple Choice Knapsack Problem”. Operations Research, May–June 1979.
V. Swaminathan, K. Chakrabarty. “Investigating the Effect of Voltage-Switching on Low-Energy Task Scheduling in Hard Real-Time Systems”. In Proc. Asia South Pacific-DAC Conference 2001.
F. Yao, A. Demers, S. Shenker. “A Scheduling Model for Reduced CPU Energy”. IEEE Annual Foundations of Computer Science, 1995.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Mejia, P., Levner, E., Mossé, D. (2003). An Integrated Heuristic Approach to Power-Aware Real-Time Scheduling. In: Falsafi, B., Vijaykumar, T.N. (eds) Power-Aware Computer Systems. PACS 2002. Lecture Notes in Computer Science, vol 2325. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36612-1_5
Download citation
DOI: https://doi.org/10.1007/3-540-36612-1_5
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-01028-9
Online ISBN: 978-3-540-36612-6
eBook Packages: Springer Book Archive