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A Low-Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics

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Power-Aware Computer Systems (PACS 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2325))

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Abstract

The effect of texture mapping in enhancing the realism of computer-generated images has made the support for real-time texture mapping a critical part of 3D graphics pipelines. However, the texture mapping is one of the major power consumers in 3D graphics pipelines due to the intensive interpolation computation and high memory bandwidth. This power consuming requires an increased emphasis on low-power design for the migration of 3D graphics systems into portable and future user interface devices. In this paper, we present a dynamically adaptive hardware texture mapping system that can perform adaptive texture mapping based on a model of human visual perception which is less sensitive to the details of moving objects. This flexibility may result in significant power savings without noticeable quality degradation. Our work shows that power savings, up to 33.9%, comes from the reduced offchip memory accesses as the result of an adaptive texel interpolation algorithm. Additional power savings, up to 73.8%, comes from using variable clock and supply voltage scaling in the adaptive computing unit.

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References

  1. A. Beers, M. Agrawala, and N. Chaddha. Rendering from compressed textures. In SIGGRAPH’ 96, 1996.

    Google Scholar 

  2. J. Blinn. Simulation of wrinkled surfaces. In SIGGRAPH’ 78, pages 286–292, 1978.

    Google Scholar 

  3. J. Blinn and M. Newell. Texture and reflection in computer generated image. Communications of the ACM, pages 542–547, October 1976.

    Google Scholar 

  4. T. Burd, T. Pering, A. Stratakos, and R. Brodersen. A dynamic voltage scaled microprocessor system. IEEE Journal of Solid-State Circuits, 35(11):68–75, November 2000.

    Google Scholar 

  5. C. J. van den Branden Lambrecht. A working spatio-temporal model of human visual system for image restoration and quality assesment applications. In International Conference on Acoustics Speech and Signal Processing, May 1996.

    Google Scholar 

  6. J. Cohen, M. Olano, and D. Manocha. Appearance-preserving simplication. In SIGGRAPH’ 98, July 1998.

    Google Scholar 

  7. M. Cox, N. Bhandari, and M. Shantz. Multi-level texture caching for 3D graphics hardware. In 25th International Symposium on Computer Architecture, June 1998.

    Google Scholar 

  8. R. Dumont, F. Pellacini, and J. Ferwerda. A perceptually-based texture caching algorithm for hardware-based rendering. In Eurographics Workshop on Rendering, pages 62–71, June 2001.

    Google Scholar 

  9. J. Euh and Wayne Burleson. Exploiting Content Variation and Perception in Power-aware 3D Graphics Rendering. Springer, 2000.

    Google Scholar 

  10. A. Gueziec, G. Taubin, F. Lazarus, and W. Horn. Simplical maps for progressive transmission of polygonal surfaces. In VRML’ 98, February 1998.

    Google Scholar 

  11. Z. Hakura and A. Gupta. The design and analysis of a cache architecture for texture mapping. In 24th International Symposium on Computer Architecture, 1997.

    Google Scholar 

  12. H. Hoppe. Progressive meshes. In SIGGRAPH’ 96, July 1998.

    Google Scholar 

  13. H. Igehy, M. Eldridge, and K. Proudfoot. Prefetching in texture cache architecture. In Eurographics/SIGGRAPH Workshop on Graphics Hardware, 1998.

    Google Scholar 

  14. D. Kelly. Motion and vision. II. stabilized spatio-temporal threshold surface. Journal of the Optical Society of America, 79(10):1340–1349, October 1979.

    Google Scholar 

  15. A. Kugler. A high-performance texturing circuit. In 25th International Symposium on Computer Architecture, pages 302–311, 1997.

    Google Scholar 

  16. T. Mitra and T. Chiueh. Dynamic 3d graphics workload charaterization and the architectural implications. In The 32nd Annual International Symposium on Microarchitecture, pages 62–71, November 1999.

    Google Scholar 

  17. R. Pajarola and J. Rossignac. Compressed progressive meshes. IEEE Transactions on Visualization and Computer Graphics, 6(1):79–93, 2000.

    Article  Google Scholar 

  18. A. Rosman and M. Pimpalkhare. United States Patent No.: US 6,184,894 B1, February 2001.

    Google Scholar 

  19. S. Venkatraman. A Power-aware Synthesizable Core for the Discrete Cosine Transform. Master Thesis, ECE Dept., UMASS Amherst, 2001.

    Google Scholar 

  20. L. Williams. Pyramidal parametrics. ACM Computer Graphics, pages 1–11, 1983.

    Google Scholar 

  21. H. Yee, S. Pattanaik, and D. Greenberg. Spatiotemporal sensitivity and visual attention for efficient rendering of dynamic environments. ACM Transactions on Graphics, 20(1), January 2001.

    Google Scholar 

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© 2003 Springer-Verlag Berlin Heidelberg

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Euh, J., Chittamuru, J., Burleson, W. (2003). A Low-Power Content-Adaptive Texture Mapping Architecture for Real-Time 3D Graphics. In: Falsafi, B., Vijaykumar, T.N. (eds) Power-Aware Computer Systems. PACS 2002. Lecture Notes in Computer Science, vol 2325. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36612-1_7

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  • DOI: https://doi.org/10.1007/3-540-36612-1_7

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-01028-9

  • Online ISBN: 978-3-540-36612-6

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