Abstract
We propose in this paper a processor architecture that supports multi instructions set through run time functional assignment algorithm (RUNFA). The above processor, which is named Functional Assignment Register Microprocessor (FaRM-rq) supports queue and register based instruction set architecture and functions into different modes: (1) R-mode (FRM) - when switched for register based instructions support, and (2) Q-mode (FQM) - when switched for Queue based instructions support. The entities share a common data path and may operate independently though not in parallel.
In FRM mode, the machine’s shared storage unit (SSU) behaves as a conventional register file. However, in FQM mode, the system organizes the SSU access as a first-in-first-out latches, thus accesses concentrate around a small window and the addressing of registers is implicit trough the Queue head and tail pointers.
First, we present the novel aspects of the FaRM-rq1 architecture. Then, we give the novel FQM fundamentals and the principles underlying the architecture.
The above architecture embraces multiprogramming languages and will combine the best features of Queue, Register and Stack models of computing.
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Okamoto S., Suzuki A., Maeda A., Sowa M.: Design of a Superscalar Processor Based on Queue Machine Computation Model. IEEE PACRIM99, (1999) 151–154
Sohi G.: Instructions Issue logic for high-performance, interruptible, Multiple Functional Unit, Pipelined Computer. IEEE Trans. on Computers, vol.39, No.3, (1990) 349–359
Abderazek B. A., Kirilka N., Sowa M.: FARM-Queue Mode: On a Practical Queue Execution model. Proc. of the Int. Conf. on Circuits and Systems, Computers and Communications, Tokushima, (2001) 939–944
Michael K. M., Harvey G.C.: Processor Implementations Using Queues. IEEE, Micro, (1995) 58–66
Philip K.: Stack Computers, the new Wave. Mountain View Press (1989)
Sowa Laboratory: http://www.sowa.is.uec.ac.jp
Bruno R., Carla V.: Data Flow on Queue Machines. 12th Int. IEEE Symposium on Computer Architecture, (1995) 342–351
Suzuki H., Shusuke O., Maeda A., Sowa M.: Implementation and evaluation of a Superscalar Processor Based on Queue Machine Computation Model. IPSJ SIG, Vol.99, No. 21 (1999) 91–96
Smith J. E., Sohi G. S.: The microarchitecture of Superscalar processors. Proceedings of the IEEE, vol. 83, (no. 12), (1995) 1609–1624
Silc J., Robic B., Ungerer T.: Processor Architecture: From Dataflow to Superscalar and Beyond. Springer-Verlag, Berlin, Heidelberg, New York (1999)
Periss B. R.: Data Flow on a Queue Machine. Doctoral thesis, Department of Electrical Engineering, University of Toronto, Toronto (1987)
Palacharia, Joupi N. P, Smith J.E: Complexity-Effective Superscalar Processor. Ph.D. dissertation, Univ. of Wisconsin (1998)
Abderazek B.A., Sowa M.: DRA: Dynamic Register Allocator Mechanism for FaRM Microprocessor. The 3rd International Workshop on Advanced Parallel Processing Technologies, IWAPPT99, (1999) 131–136
Abderazek B.A.: Dynamic Instructions Issue Algorithm and a Queue Execution Model Toward the Design of a Hybrid Processor Architecture. PhD. Thesis, IS Graduate School, Univ. of Electro-Communications, (2002)
Sowa M.: Fundamental of Queue machine. The Univ. of Electro-Communications, Sowa Laboratory, Technical Reports SLL30305, (2003)
Radhakrishnan R., Talla D., John L. K.: Allowing for ILP in an Embedded Java Processor. Proceedings of IEEE/ACM International Symposium on Computer Architecture, Vancouver, CA, (2000) 294–305
Sowa M.: Queue Processor Instruction Set Design. The Univ. of Electro-Communications, Sowa laboratory, Technical Report SLL97301, (1997)
Sowa M., Abderazek B.A, Shigeta S., Nikolova K., D. Yoshinaga T. Proposal and Design of a Parallel Queue Processor Architecture (PQP), 14th IASTED Int. Conf. on Parallel and Distributed Computing and System, Cambridge, USA, (2002) 554–560
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Abderazek, B.A., Shigeta, S., Yoshinaga, T., Sowa, M. (2003). On the Design of a Register Queue Based Processor Architecture (FaRM-rq). In: Guo, M., Yang, L.T. (eds) Parallel and Distributed Processing and Applications. ISPA 2003. Lecture Notes in Computer Science, vol 2745. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-37619-4_26
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DOI: https://doi.org/10.1007/3-540-37619-4_26
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