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International Symposium on High Performance Computing

ISHPC 2000: High Performance Computing pp 7–25Cite as

Macroservers: An Object-Based Programming and Execution Model for Processor-in-Memory Arrays

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1940))

Abstract

The emergence of semiconductor fabrication technology allowing a tight coupling between high-density DRAM and CMOS logic on the same chip has led to the important new class of Processor-in-Memory (PIM) architectures. Recent developments provide powerful parallel processing capabilities on the chip, exploiting the facility to load wide words in single memory accesses and supporting complex address manipulations in the memory. Furthermore, large arrays of PIMs can be arranged into massively parallel architectures. In this paper, we outline the salient features of PIM architectures and describe the design of an object-based programming and execution model centered on the notion of macroservers. While generally adhering to the conventional framework of object-based computation, macroservers provide special support for the efficient control of program execution in a PIM array. This includes features for specifying the distribution and alignment of data in virtual object space, the binding of threads to data, and a future-based synchronization mechanism. We provide a number of motivating examples and give a short overview of implementation considerations.

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Author information

Authors and Affiliations

  1. Institute for Software Science, University of Vienna, Austria

    Hans P. Zima

  2. Center for Advanced Computing Research (CACR), California Institute of Technology, Pasadena, California, U.S.A.

    Thomas L. Sterling

Authors
  1. Hans P. Zima
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  2. Thomas L. Sterling
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Editor information

Editors and Affiliations

  1. Departamento de Arquitectura de Computadores, Universidad Politecnica de Catalunya, Spain

    Mateo Valero

  2. Department of Information and Computer Sciences, Nara Women’s University, Japan

    Kazuki Joe

  3. Institute of Industrial Science Center for Conceptual Information Processing Research, University of Tokyo, Japan

    Masaru Kitsuregawa

  4. Graduate School of Engineering Electrical Engineering Department, University of Tokyo, Japan

    Hidehiko Tanaka

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© 2000 Springer-Verlag Berlin Heidelberg

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Zima, H.P., Sterling, T.L. (2000). Macroservers: An Object-Based Programming and Execution Model for Processor-in-Memory Arrays. In: Valero, M., Joe, K., Kitsuregawa, M., Tanaka, H. (eds) High Performance Computing. ISHPC 2000. Lecture Notes in Computer Science, vol 1940. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-39999-2_2

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  • DOI: https://doi.org/10.1007/3-540-39999-2_2

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-41128-4

  • Online ISBN: 978-3-540-39999-5

  • eBook Packages: Springer Book Archive

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