Abstract
Simulation-based Fault Injection in VHDL descriptions is increasingly common due to the popularity of top-down design flows exploiting this language. This paper presents some techniques for reducing the time to perform the required simulation experiments. Static and dynamic methods are proposed to analyze the list of faults to be injected, removing faults as soon as their behavior is known. Common features available in most VHDL simulation environments are also exploited. Experimental results show that the proposed techniques are able to reduce the time required by a typical Fault Injection campaign by a factor ranging from 43.9% to 96.6%.
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Parrotta, B., Rebaudengo, M., Reorda, M.S., Violante, M. (2000). Speeding-Up Fault Injection Campaigns in VHDL Models. In: Koornneef, F., van der Meulen, M. (eds) Computer Safety, Reliability and Security. SAFECOMP 2000. Lecture Notes in Computer Science, vol 1943. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-40891-6_3
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DOI: https://doi.org/10.1007/3-540-40891-6_3
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