Abstract
This paper describes a high bandwidth and low latency hybrid wavepipelined data bus scheme for multi-bank DRAM macros on single chip multiprocessors. Long data bus lines inserted with multiple wave-pipelined stages at each bank input/output are further divided by periodically inserted synchronizing registers to overcome cycle time degradations due to skew and jitter effects in the wave-pipe. Each memory macro controller controls the access sequence not only to avoid internal bank access conflicts, but also to communicate with the other controllers through the hybrid bus. A SPICE simulation result is shown assuming for a 64Mbit macro comparing four 128bit wide data bus schemes. The hybrid scheme can realize over 1GHz on-die data bus for multi-bank DRAM.
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Ogawa, J., Horowitz, M. (2001). A 64Mbit Mesochronous Hybrid Wave Pipelined Multibank DRAM Macro. In: Chong, F.T., Kozyrakis, C., Oskin, M. (eds) Intelligent Memory Systems. IMS 2000. Lecture Notes in Computer Science, vol 2107. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44570-6_1
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DOI: https://doi.org/10.1007/3-540-44570-6_1
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