Abstract
Merging processors and memory into a single chip has the well-known benefits of allowing high-bandwidth and low-latency communication between processor and memory, and reducing energy consumption. As a result, many different systems based on what has been called Processor In Memory (PIM) architectures have been proposed [1, 3, 7, 8, 10, 12-16, 18].
Recent advances in technology [4, 5] appear to make it possible to integrate logic that cycles nearly as fast as in a logic-only chip. As a result, processors are likely to put much pressure on the relatively slow on-chip DRAM. To handle the speed mismatch between processors and DRAM, these chips are likely to include non-trivial memory hierarchies in each DRAM bank.
With many on-chip high-frequency processors, all of them potentially accessing the memory system concurrently, these chips will consume much energy. In addition, these chips are likely to be used in non-traditional places like the memory of a server [3, 7,
In this abstract, we examine, from a performance and energy-efficiency point of view, the design of the memory hierarchy in a multi-banked PIM chip with many simple, fast processors. Our results suggest the use of per-processor memory hierarchies that include modest-sized caches, simple DRAM bank organizations that support segmentation, and no prefetching.
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Huang, M., Renau, J., Yoo, SM., Torrellas, J. (2001). Energy/Performance Design of Memory Hierarchies for Processor-in-Memory Chips⋆. In: Chong, F.T., Kozyrakis, C., Oskin, M. (eds) Intelligent Memory Systems. IMS 2000. Lecture Notes in Computer Science, vol 2107. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44570-6_11
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DOI: https://doi.org/10.1007/3-540-44570-6_11
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