Skip to main content
SpringerLink
Log in

Implementation of Virtual Circuits by Means of the FIPSOC Devices

  • Conference paper
  • First Online:
Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing (FPL 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1896))

Included in the following conference series:

  • 625 Accesses

Abstract

This paper will explain a systematic technique for the implementation of a synchronous circuit into the DRFPGA (dynamic reconfigurable FPGA) included in the FIPSOC devices, taking advantage of their properties of dynamic reconfiguration. The circuit to be implemented is partitioned using a set of temporal bipartitioning rules, and each partition is mapped on a separated context, sharing both contexts the same hardware resources. The time-multiplexed execution of both contexts constitutes a virtual circuit.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. J.M. Moreno, J. Madrenas, J. Cabestany, E. Cantó, R. Kielbik, J. Faura, J.M. Insenser, “Realization of Self-Repairing and Evolvable Harware Structures by Means of Implicit Self-Configuration“, Proceedings of the First NASA/DoD Workshop on Evolvable Hardware (EH’99), pp. 182–187, Pasadena, California, July 1999.

    Google Scholar 

  2. J.M. Moreno, J. Madrenas, J. Faura, E. Cantó, J. Cabestany, J.M. Insenser, “Feasible Evolutionary and Self-Repairing Hardware by Means of the Dynamic Reconfiguration Capabilities of the FIPSOC Devices”, Evolvable Systems: From Biology to Hardware, M. Sipper, D. Mange, A. Pérez-Uribe (eds.), pp. 345–355, Springer-Verlag, 1998.

    Google Scholar 

  3. J. Madrenas, J.M. Moreno, J. Cabestany, J. Faura, J.M. Insenser, “Radiation-Tolerant On-Line Monitored MAC Unit for Neural Models Using Reconfigurable-Logic FIPSOC Devices”, 4th IEEE International On-Line Test Workshop, pp. 114–118, Capri, Italy, July 1998.

    Google Scholar 

  4. J.M. Moreno, J. Madrenas, J. Cabestany, E. Cantó, J. Faura, J.M. Insenser, “Dynamically Reconfigurable Strategies for Implementing Artificial Neural Networks Models in Programmable Hardware“, Proceedings of the 6th Conference Mixed Designs of Integrated Circutis and Systems (MIXDES’99), pp. 379–384, Kraków, Poland, June 1999.

    Google Scholar 

  5. J.M. Moreno, J. Cabestany, E. Cantó, J. Faura, J.M. Insenser, “The Role of Dynamic Reconfiguration for Implementing Artificial Neural Networks Models in Programmable Hardware”, Engineering Applications of Bio-Inspired Artificial Neural Networks, J. Mira, J.V. Sánchez Andrés (eds.), pp. 85–94, Springer-Verlag, 1999.

    Google Scholar 

  6. J. Faura, C. Horton, P. van Doung, J. Madrenas, J.M. Inserser, “A Novel Mixed Signal Programmable Device with On-Chip Microprocessor”. Proceedings of the IEEE 1997 Custom Integrated Circuits Conference (1997) 103–106.

    Google Scholar 

  7. J. Faura, J.M. Moreno, M-A. Aguirre, P. Van Doung, J.M. Insenser, “Multicontext Dynamic Reconfiguration and Real-Time Probing on a Novel Mixed Signal Programmable Device with On-Chip Microprocessor”, Field-Programmable Logic and Applications, W. Luk, Y.K. Cheung, M. Glesner (eds.) pp. 1–10, Springer-Verlag, 1997.

    Google Scholar 

  8. Michael J. Wirthlin, Brad L. Hutchings, “Improving Functional Density Using Run-Time Circuit Reconfiguration”. IEEE Transactions on VLSI Systems, Vol. 6, No. 2, pp. 247–256, June 1998.

    Article  Google Scholar 

  9. Huiqun Liu and D.F. Wong, “Circuit Partitioning for Dynamically Reconfigurable FPGAs”. International Symposium on Field Programmable Gate Arrays, Monterrey, CA, pp. 187–194, Feb. 1999.

    Google Scholar 

  10. Steve Trimberger, “Scheduling Designs into a Time-Multiplexed FPGA”, International Symposium on Field Programmable Gate Arrays, pp. 153–160, Feb. 98

    Google Scholar 

  11. D. Chang, M. Marek-Sadowska, “Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs”, International Symposium on Field Programmable Gate Arrays, pp. 161–167, Feb. 98

    Google Scholar 

  12. D. Chang, M. Marek-Sadowska, “Partitioning Sequential Circuits on Dynamically Reconfigurable FPGAs”, IEEE Transatcions on Computers, Vol. 48, No. 6, pp. 565–578, June 1999.

    Article  MathSciNet  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Departament of Electronics Engineering, Technical University of Catalunya (UPC), c/ Gran Capitá s/n, 08034, Barcelona, Spain

    E. Cantó, J. M. Moreno & J. Cabestany

  2. SIDSA, PTM, Torres Quevedo 1, 28760, Tres Cantos (Madrid), Spain

    I. Lacadena & J. M. Insenser

Authors
  1. E. Cantó
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. J. M. Moreno
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. J. Cabestany
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. I. Lacadena
    View author publications

    You can also search for this author in PubMed Google Scholar

  5. J. M. Insenser
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Computer Science Department, University of Kaiserslautern, P. O. Box. 30 49, 67653, Kaiserslautern, Germany

    Reiner W. Hartenstein

  2. Carinthia Tech Institute, Richard-Wagner-Str. 19, 9500, Villach, Austria

    Herbert Grünbacher

Rights and permissions

Reprints and permissions

Copyright information

© 2000 Springer-Verlag Berlin Heidelberg

About this paper

Cite this paper

Cantó, E., Moreno, J.M., Cabestany, J., Lacadena, I., Insenser, J.M. (2000). Implementation of Virtual Circuits by Means of the FIPSOC Devices. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_10

Download citation

  • DOI: https://doi.org/10.1007/3-540-44614-1_10

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67899-1

  • Online ISBN: 978-3-540-44614-9

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation