Verification of Dynamically Reconfigurable Logic

Abstract

Conventional FPGA design assumes a one-to-one mapping between circuits and device resources. In contrast, dynamically reconfigurable designs map many circuits to shared device resources. Each many-to-one mapping can be decomposed into sequences of temporal, one-to-one mappings. The verification of dynamically reconfigurable logic is complicated by the need to verify that each constituent mapping is correct and that its sequencing with respect to time and other circuits is also correct. In this paper, we introduce new design tools for verifying dynamically reconfigurable logic. The tools extend the capabilities of the Dynamic Circuit Switching (DCS) CAD framework for dynamically reconfigurable logic. The verification capabilities include new design rule checks, design violation monitoring, and the extension of coverage analysis and performance profiling techniques to dynamically reconfigurable designs.