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Self-Testing of Linear Segments in User-Programmed FPGAs

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Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing (FPL 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1896))

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Abstract

A method for the development of a test plan for BIST-based exhaustive testing of a circuit implemented with an in-system reconfigurable FPGA is presented. A test plan for application-dependent testing of an FPGA is based on the concept of a logic cone and linear segment. Linear segments that satisfy single-or multi-generator compatibility requirement can be combinationally-exhaustively tested concurrently and are merged into a test block. Two methods for merging logic cones and linear segments are proposed. Experimental results are presented.

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References

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Author information

Authors and Affiliations

  1. Warsaw University of Technology, Nowowiejska 15/19, 00-665, Warsaw, Poland

    Pawel Tomaszewicz

Authors
  1. Pawel Tomaszewicz
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Editor information

Editors and Affiliations

  1. Computer Science Department, University of Kaiserslautern, P. O. Box. 30 49, 67653, Kaiserslautern, Germany

    Reiner W. Hartenstein

  2. Carinthia Tech Institute, Richard-Wagner-Str. 19, 9500, Villach, Austria

    Herbert Grünbacher

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© 2000 Springer-Verlag Berlin Heidelberg

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Tomaszewicz, P. (2000). Self-Testing of Linear Segments in User-Programmed FPGAs. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_19

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  • DOI: https://doi.org/10.1007/3-540-44614-1_19

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67899-1

  • Online ISBN: 978-3-540-44614-9

  • eBook Packages: Springer Book Archive

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