Abstract
As integration levels in FPGA devices have increased over the past decade, the structure of programmable logic resources has become more diversified. Recently, Altera Corporation has introduced a new family of LUT-based FPGAs that have been augmented with user-configurable programmable logic array blocks (PLAs). In this paper a novel FPGA technology mapping approach is described that automatically partitions user designs into netlist subgraphs appropriately-sized for implementation on both types of available user resources. The subgraphs are subsequently mapped to assigned target resources. It is shown that fast estimation of post-minimization product term counts plays an especially important role in the mapping of designs to PLAs.
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Krishnamoorthy, S., Swaminathan, S., Tessier, R. (2000). Area-Optimized Technology Mapping for Hybrid FPGAs. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_21
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DOI: https://doi.org/10.1007/3-540-44614-1_21
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