Abstract
Internet Protocol (IP) characterization is the process of classifying IP packets into categories, mainly depending on information in the header. This report describes the implementation of an FPGA-based dynamically reconfigurable Content Addressable Memory (CAM) for IP version 6 (IPv6) characterization. This CAM is characterized by a large width of the search word, a relatively small number of CAM words (i.e. several 100’s) and the fact that these words may contain ‘don’t cares’. The CAM is updated by dynamic reconfiguration and has a novel architecture that allows the space, that each single CAM word occupies, to be variable. A priority mechanism has been developed which allows also to explicitly assign a priority to a CAM entry. This way, CAM words can be added/deleted in a more efficient way.
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Ditmar, J., Torkelsson, K., Jantsch, A. (2000). A Dynamically Reconfigurable FPGA-Based Content Addressable Memory for Internet Protocol Characterization. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_3
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DOI: https://doi.org/10.1007/3-540-44614-1_3
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