Abstract
An FPGA based Artificial Neural Network is proposed. The neuron is based on a spiking scheme where signals are encoded in a stochastic pulse train. The neuron is composed of a synaptic module and a summing-activation module. The architecture of the neuron is characterized and its FPGA implementation is presented. The basic spiking neuron is used to implement a basic neural network. An extension of the neuron architecture to include an address-event protocol for signal multiplexing in a single line is proposed. VHDL simulations and FPGA synthesis results are discussed.
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References
IEEE Transactions on Neural Networks. “Special issue on pulse coupled neural networks”, Vol. 10, No. 3 (1999)
Bade, S. and Hutchings, B.: FPGA-Based Stochastic Neural-Implementation. IEEE Workshop on FPGAs for Custom Computing Machines, Napa, CA, (1994) 189–198
Beuchat, J.-L.: Réalisation materielle de réseaux neuronaux en logique stochastique. Technical Report, (1996) http://diwww.epfl.ch/~jlbeucha/neural_html/projet2.html
Moerland, P. and Fiesler, E.: Neural network adaptations to hardware implementations. Handbook of neural computation, release 97/1, IOP Publishing Ltd and Oxford University Press, (1997)
Hikawa, H.: Frequency-Based Multilayer Neural Network with On-Chip Learning and Enhancement Neuron Characteristics. Transactions on Neural Networks IEEE, Vol. 10, No. 3, (1999) 545–553
Hikawa, H.: Learning Performance of Frequency-Modulation Digital Neural Network with On-Chip Learning. WCCI’ 98 — IJCNN (1998) 557–562
Lazzaro, J., Wawrzynek, J., Mahowald, M., Sivilotti, M., Gillespie, D.: Silicon auditory processors as computer peripherals. IEEE Transactions On Neural Networks, Vol. 4, No. 3, (1993) 523–527
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© 2000 Springer-Verlag Berlin Heidelberg
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Maya, S., Reynoso, R., Torres, C., Arias-Estrada, M. (2000). Compact Spiking Neural Network Implementation in FPGA. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_30
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DOI: https://doi.org/10.1007/3-540-44614-1_30
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