A Parallel Pipelined SAT Solver for FPGA’s

Abstract

Solving Boolean satisfiability problems in reconfigurable hardware is an area of great research interest. Originally, reconfigurable hardware was used to map each problem instance and thus exploit maximum parallelism in evaluation of variable assignments. However, techniques to greatly reduce the search space require dynamic reconfiguration, and make regular mappings more desirable. Unfortunately, using a regular mapping constrains the parallelism in assignment evaluation. The architectures that have emerged choose either custom mapping and maximum parallelism or regular mapping and the promise of significant decreases in the search space. We propose a framework that can exploit both. Our framework uses a regular mapping while introducing a scalable parallel architecture. Using our approach, speedups of up to one order of magnitude over current state-of-the-art reconfigurable hardware solvers have been obtained.

This research was performed as part of the MAARCII project. This work is supported by the DARPA Adaptive Computing Systems program under contract no. DABT63-99-1-0004 monitored by Fort Huachuca