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Memory Access Schemes for Configurable Processors

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Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing (FPL 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1896))

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Abstract

This work discusses theMemoryArchitecture for Reconfigurable Computers (MARC), a scalable, device-independent memory interface that supports both irregular (via configurable caches) and regular accesses (via pre-fetching stream buffers). By hiding specifics behind a consistent abstract interface, it is suitable as a target environment for automatic hardware compilation.

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Author information

Authors and Affiliations

  1. Tech. Univ. Braunschweig (E.I.S.), Gaußstr. 11, D-38106, Braunschweig, Germany

    Holger Lange & Andreas Koch

Authors
  1. Holger Lange
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  2. Andreas Koch
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Editor information

Editors and Affiliations

  1. Computer Science Department, University of Kaiserslautern, P. O. Box. 30 49, 67653, Kaiserslautern, Germany

    Reiner W. Hartenstein

  2. Carinthia Tech Institute, Richard-Wagner-Str. 19, 9500, Villach, Austria

    Herbert Grünbacher

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© 2000 Springer-Verlag Berlin Heidelberg

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Lange, H., Koch, A. (2000). Memory Access Schemes for Configurable Processors. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_66

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  • DOI: https://doi.org/10.1007/3-540-44614-1_66

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67899-1

  • Online ISBN: 978-3-540-44614-9

  • eBook Packages: Springer Book Archive

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