Abstract
We present an extension of a procedure for self-testing of an FPGA that implements a user-defined function. This extension, intended to improve the detectability of FPGA delay faults, exploits the reconfigurability of FPGAs and is based on modifying the functions of LUTs in the section under test. A modification procedure replaces a user-defined function of each LUT with a specific function that preserves the blocking capability and input-output transition pattern of the original function. We show that the proposed method significantly increases the susceptibility of FPGA delay faults to random testing.
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© 2000 Springer-Verlag Berlin Heidelberg
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Krasniewski, A. (2000). Exploiting Reconfigurability for Effective Detection of Delay Faults in LUT-Based FPGAs. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_72
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DOI: https://doi.org/10.1007/3-540-44614-1_72
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