Abstract
In the ConCISe project, an embedded programmable processor is augmented with a Reconfigurable Functional Unit (RFU) based on Field-Programmable Logic (FPL), in a technique that aims at being cost-effective for high volume production. The target domain is embedded encryption. In this paper, we focus on ConCISe’s programming tool-set. A smart assembler, capable of automatically performing HW/SW partitioning and HW synthesis, generates the custom operations that are implemented in the RFU. Benchmarks carried out with ConCISe’s simulators show that the RFU may speed up off-the-shelf encryption applications by as much as 50%, for a modest investment in silicon, and with no changes in the traditional application programming flow.
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References
B. Kastrup et al. “ConCISe: A Compiler-Driven, CPLD-Based Instruction Set Accelerator”. Proc. of the IEEE Intl. Symp. On Field-Programmable Custom Computing Machines, FCCM ‘99, Napa, CA, 1999.
R. Razdan and M.D. Smith. “A High-Performance Microarchitecture with Hardware-Programmable Functional Units”, Proc. 27th Annual IEEE/ACM Intl. Symp. On Microarchitecture, MICRO-27, November 1994.
S. Sawitzki et al. “Increasing Microprocessor Performance with Tightly-Coupled Reconfigurable Logic Arrays”, Proc. of Field-Programmable Logic and Applications, FPL ‘98, Tallinn, Estonia, August/September, 1998.
XCR3960, 960 macrocell SRAM CPLD. Data Sheet, July 1998. http://www.xilinx.com/partinfo/xcr3960.pdf
C. Alippi et al. “A DAG-Based Design Approach for Reconfigurable VLIW Processors”, Proc. Of IEEE Design and Test Conference in Europe, Munich, March 1999.
B. Schneier. “Applied Cryptography: Protocols, Algorithms and Source Code in C”, Second Edition, John Wiley & Sons, Inc., 1996.
http://www.btinternet.com/~brian.gladman/cryptography_technology/aes/index.html
B. Kastrup and O. Moreira. “A Novel Approach to Minimising the Logic of Combinatorial Multiplexing Circuits in Product-Term-Based Hardware”, Proc. of EUROMICRO Symp. On Digital Systems Design (IEEE Computer Society Press), Maastricht, September 2000.
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© 2000 Springer-Verlag Berlin Heidelberg
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Kastrup, B., Trum, J., Moreira, O., Hoogerbrugge, J., van Meerbergen, J. (2000). Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_74
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DOI: https://doi.org/10.1007/3-540-44614-1_74
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