Abstract
In the ConCISe project, an embedded programmable processor is augmented with a Reconfigurable Functional Unit (RFU) based on Field-Programmable Logic (FPL), in a technique that aims at being cost-effective for high volume production. The target domain is embedded encryption. In this paper, we focus on ConCISe’s programming tool-set. A smart assembler, capable of automatically performing HW/SW partitioning and HW synthesis, generates the custom operations that are implemented in the RFU. Benchmarks carried out with ConCISe’s simulators show that the RFU may speed up off-the-shelf encryption applications by as much as 50%, for a modest investment in silicon, and with no changes in the traditional application programming flow.
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References
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© 2000 Springer-Verlag Berlin Heidelberg
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Kastrup, B., Trum, J., Moreira, O., Hoogerbrugge, J., van Meerbergen, J. (2000). Compiling Applications for ConCISe: An Example of Automatic HW/SW Partitioning and Synthesis. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_74
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DOI: https://doi.org/10.1007/3-540-44614-1_74
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