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Divider Circuit Verification with Model Checking and Theorem Proving

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Theorem Proving in Higher Order Logics (TPHOLs 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1869))

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Abstract

Most industrial-size hardware verification problems are amenable to neither fully automated nor fully manual hardware verification methods. However, combinations of these two extremes, human-constructed proofs with automatically verified lower-level steps, seem to offer great promise. In this paper we discuss a formal verification case study based on such a combination of theorem-proving and model-checking techniques. The case study addresses the correctness of a floating-point divider unit of an Intel IA-32 microprocessor.

The verification was carried out in the Forte framework, which consists of a general-purpose theorem-prover, ThmTac, on top of a symbolic trajectory evaluation based model-checking engine. The correctness of the circuit was formulated and decomposed to smaller, automatically model-checkable, statements in a pre/postcondition framework. The other key steps of the proof involved relating bit vectors to integer arithmetic and general arithmetic reasoning.

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Kaivola, R., Aagaard, M.D. (2000). Divider Circuit Verification with Model Checking and Theorem Proving. In: Aagaard, M., Harrison, J. (eds) Theorem Proving in Higher Order Logics. TPHOLs 2000. Lecture Notes in Computer Science, vol 1869. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44659-1_21

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  • DOI: https://doi.org/10.1007/3-540-44659-1_21

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67863-2

  • Online ISBN: 978-3-540-44659-0

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