An Introduction to the Gilgamesh PIM Architecture

Abstract

Throughout the history of computer implementation, the technologies employed for logic to build ALUs and the technologies employed to realize high speed and high-density storage for main memory have been disparate, requiring different fabrication techniques. This was certainly true at the beginning of the era of electronic digital computers where logic was constructed from vacuum tubes and main memory was produced by wired arrays of magnetic cores. But it is also true with today’s conventional computing systems. Yes, both logic and memory are now fabricated with semiconductors. But the fabrication processes are quite different as they are optimized for very different functionality. CMOS logic pushes speed of active components while DRAM storage maximizes densityof passive capacitive bit cells. As a consequence of this technology disparity between the means of achieving distinct capabilities of memory and logic, computer architecture has been constrained by the separation of logical units and main memory units. The von Neumann bottleneck is the communication’s channel choke point between CPUs and main memory resulting from the separation imposed by these distinct device types. Much of modern microprocessor architecture is driven by the resulting data transfer throughput and latency of access due to this separation as well as the very different clock speeds involved. More subtle but of equal importance are the limitations imposed on the diversity of possible structures that might be explored and achieved were it feasible to bridge this gap and intertwine memory and logic.

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