Abstract
In this paper, a FPGA implementation is presented to carry out the conversion process from NURBS to Bézier curves. It has a simple and regular timing schedule with a constant latency which reduces the area requirements with respect to previous implementations. The operation frequency obtained with the Xilinx tools, is around 13 MHz. The scheme we propose can be easily extended to process NURBS and Bézier surfaces.
This work was supported in part by the Secretaria Xeral de Investigacion e Desenvolvemento de Galicia (Spain) under contract PGIDT99-PXI20602B.
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© 2001 Springer-Verlag Berlin Heidelberg
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Mallón, P.N., Bóo, M., Bruguera, J.D. (2001). Implementation of a NURBS to Bézier Conversor with Constant Latency. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_22
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DOI: https://doi.org/10.1007/3-540-44687-7_22
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