Abstract
In this paper, we present a new placement method which provides short implementation times for today’s high capacity FPGAs within a direct mapping environment. We show that using additional component information is beneficial for faster logic block placement. The new placement method reduces the placer’s run time by taking the module in- and output interconnections into account.
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Abke, J., Barke, E. (2001). A New Placement Method for Direct Mapping into LUT-Based FPGAs. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_4
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DOI: https://doi.org/10.1007/3-540-44687-7_4
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