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Dynamically Reconfigurable Cores

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Field-Programmable Logic and Applications (FPL 2001)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2147))

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Abstract

Dynamic reconfiguration of digital circuits on FPGAs has been an area of active research for the past decade. The identification of generic classes of circuits that would benefit from being dynamically reconfigured remains a key, open problem. We report on an investigation of the application of dynamic reconfiguration to programmable, multi-function cores (PMCs). An abstract analysis of the technique is included to emphasise the generality of the methodology. Empirical results for a case study involving a universal asynchronous receiver and transmitter (UART) are presented. We show that significant improvements in area efficiency and the operating speeds of the circuits are achieved. Furthermore, the results indicate the potential for reducing the power consumption of the circuits.

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Authors and Affiliations

  1. Dept. Electronic and Electrical Engineering, University of Strathclyde, 204 George Street, Glasgow, G1 1XW, UK

    John MacBeth & Patrick Lysaght

Authors
  1. John MacBeth
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  2. Patrick Lysaght
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Editors and Affiliations

  1. Division of Informatics, University of Edinburgh, James Clerk Maxwell Building Mayfield Road, EH9 3JZ, Edinburgh, UK

    Gordon Brebner

  2. School of Electrical and Electronic Engineering, Queen’s University of Belfast, Ashby Building Stranmillis Road, BT9 5AH, Belfast, UK

    Roger Woods

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© 2001 Springer-Verlag Berlin Heidelberg

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MacBeth, J., Lysaght, P. (2001). Dynamically Reconfigurable Cores. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_48

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  • DOI: https://doi.org/10.1007/3-540-44687-7_48

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-42499-4

  • Online ISBN: 978-3-540-44687-3

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