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Parameterized Function Evaluation for FPGAs

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Field-Programmable Logic and Applications (FPL 2001)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2147))

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Abstract

This paper presents parameterized module-generators for pipelined function evaluation using lookup tables, adders, shifters and multipliers. We discuss trade-offs involved between (1) full-lookup tables, (2) bipartite (lookup-add) units, (3) lookup-multiply units, and (4) shift-and-add based CORDIC units. For lookup-multiply units we provide equations estimating approximation errors and rounding errors which are used to parameterize the hardware units. The resources and performance of the resulting design can be estimated given the input parameters. The method is implemented as part of the PAM-Blox module generation environment. An example shows that the lookup-multiply unit produces competitive designs with data widths up to 20 bits when compared with shift-and-add based CORDIC units. Additionally, the lookup-multiply method can be used for larger data widths when evaluating functions not supported by CORDIC.

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References

  1. H.M. Ahmed, Signal Processing Algorithms and Architectures, PhD Thesis, E.E. Department, Stanford University, June 1982.

    Google Scholar 

  2. R. Andraka, “A Survey of CORDIC Algorithms for FPGAs,” Proc. ACM/SIGDA Int. symp. Field Programmable Gate Arrays, ACM Press, pp. 191–200, 1998.

    Google Scholar 

  3. N. Boullis, Designing Arithmetic Units for Adaptive Computing with PAM-Blox, MIM Internship Report, ENS-Lyon, France, Sept. 2000.

    Google Scholar 

  4. C. Ebeling, D.C. Cronquist, P. Franklin, J. Secosky and S.G. Berg, “Mapping Applications to the RaPiD Configurable Architecture,” Proc. IEEE Symp. on FPGAs for Custom Computing Machines, Computer Society Press, pp. 106–115, 1997.

    Google Scholar 

  5. R. Laufer, R.R. Taylor and H. Schmit, “PCI-PipeRench and SWORD API: A System for Stream-based Reconfigurable Computing,” Proc. IEEE Symp. on FPGAs for Custom Computing Machines, IEEE Computer Society Press, pp. 200–208, 1999.

    Google Scholar 

  6. O. Mencer, Rational Arithmetic Units in Computer Systems, PhD Thesis (with M.J. Flynn), E.E. Dept., Stanford University, Jan. 2000.

    Google Scholar 

  7. O. Mencer, H. Huebert, M. Morf and M.J. Flynn, “StReAm: Object-Oriented Programming of Stream Architectures using PAM-Blox”, Field-Programmable Logic and Applications, LNCS 1896, Springer, pp. 595–604, 2000.

    Google Scholar 

  8. O. Mencer, M. Morf and M.J. Flynn, “PAM-Blox: High Performance FPGA Design for Adaptive Computing,” Proc. IEEE Symp. on FPGAs for Custom Computing Machines, IEEE Computer Society Press, pp. 167–174, 1998.

    Google Scholar 

  9. O. Mencer, L. Séméria, M. Morf and J.M. Delosme, “Application of Reconfigurable CORDIC Architectures,” Journal of VLSI Signal Processing, Vol. 24, No. 2-3, pp. 211–221, March 2000.

    Google Scholar 

  10. J.M. Muller, Elementary Functions, Algorithms and Implementation, Birkhaeuser, Boston, 1997.

    Google Scholar 

  11. S. Rixner et al., “A Bandwidth-Efficient Architecture for Media Processing,” Proc. ACM/IEEE Int’l Symposium on Microarchitecture, IEEE Computer Society Press, pp. 3–13, 1998.

    Google Scholar 

  12. M.J. Schulte and J.E. Stine, “Approximating Elementary Functions with Symmetric Bipartite Tables”, IEEE Trans. Comput., Vol. 48, No. 8, pp. 842–847, August 1999.

    Article  Google Scholar 

  13. P.T.P. Tang, “Table Lookup Algorithms for Elementary Functions and Their Error Analysis,” Proc. 10th IEEE Symp. Computer Arithmetic, IEEE Press, pp. 232–236, 1991.

    Google Scholar 

  14. J.E. Volder, “The CORDIC Trigonometric Computing Technique,” IRE Trans. on Electronic Computers, Vol. EC-8, No. 3, Sept. 1959.

    Google Scholar 

  15. M. Weinhardt and W. Luk, “Pipeline Vectorization,” IEEE Trans. Comput. Aided Design, Vol. 20, No. 2, pp. 234–248, February 2001.

    Article  Google Scholar 

  16. W.F. Wong and E. Goto, “Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers,” IEEE Trans. Comput., Vol. 43, pp. 278–294, March 1994.

    Google Scholar 

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© 2001 Springer-Verlag Berlin Heidelberg

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Mencer, O., Boullis, N., Luk, W., Styles, H. (2001). Parameterized Function Evaluation for FPGAs. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_56

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  • DOI: https://doi.org/10.1007/3-540-44687-7_56

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-42499-4

  • Online ISBN: 978-3-540-44687-3

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