Abstract
Constant coefficient multiplication using look-up tables is a popular form of multiplication in FPGAs. The ample look-up table resources found within the FPGA match well to the architecture of a look-up table based multiplier. While this form of multiplication maps well to FPGAs, it isn’t particularly efficient. This paper presents an efficient variant of this multiplier using the advanced features of the Xilinx Virtex FPGA. Specifically, this approach combines the look-up and add operations required by this multiplier architecture.
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References
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Wirthlin, M.J., McMurtrey, B. (2001). Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_57
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DOI: https://doi.org/10.1007/3-540-44687-7_57
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