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Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures

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Field-Programmable Logic and Applications (FPL 2001)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2147))

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Abstract

Application-specific Systems-on-Chip (SoCs) introduce a set of various challenges for their interdisciplinary microelectronic implementation, from system theory (application) level over efficient CAD methods to suitable technologies, e. g. considering also reconfigurable hardware parts on different granularities. The paper sketches first major perspectives in architecture, design and application of Configurable Systems-on-Chip (CSoCs). The focus is the description of new CAD-algorithms for mapping automatized presynthesized IP-cores onto coarsegrain dynamically reconfigurable array architectures. Here, combinatorial optimization methods are combined with physical chip design algorithms, whereas dynamic reconfiguration of allocated hardware resources is considered.

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References

  1. “ASIC Sstem-on-a-Chip”, Integrated Circuit Engineering (ICE), http://www.ice-corp.com

  2. M. Glesner, J. Becker, T. Pionteck: Future Research, Application and Education Perspectives of Complex Systems-on-Chip (Sot); in: Proc. of Baltic Electronic Conference (BEC 2000), October 2000, Tallinn, Estonia

    Google Scholar 

  3. P. Athanas, A. Abbot: Real-Time Image Processing on a Custom Computing Platform, IEEEComputer, vol. 28, no. 2, Feb. 1995.

    Google Scholar 

  4. R. W. Hartenstein, J. Becker et al.: A Novel Machine Paradigm to Accelerate Scientific Computing; Special issue on Scientific Computing of Computer Science and Informatics Journal, Computer Society of India, 1996.

    Google Scholar 

  5. J. Rabaey, “Reconfigurable Processing: The Solution to Low-Power Programmable DSP”, Proceedings ICASSP 1997, Munich, pp., April 1997.

    Google Scholar 

  6. J. Becker, et aL: DReAM: A Dynamically Reconfigurable Architecture for Future Mobile Communication Applications; in: 10th Int’l. Conf. on Field Programmable Logic and Applications, Villach, Österreich

    Google Scholar 

  7. J. Becker, M. Glesner: IP-based Application Mapping Techniques for Dynamically Reconfigurable Hardware Architectures; Proc. Int’l. WS on Eng. of Reconf. HW/SW Objects (ENREGLE’OO), June 2000, Las Vegas, USA.

    Google Scholar 

  8. Y. Zorian, R. K. Gupta: Design and Test of Core-Based Systems on Chips; in IEDesign & Test of Computers, pp. 14–25, Oct.–Dec. 1997.

    Google Scholar 

  9. Xilinx Corp.: http://www.xilinx.com/products/virtex.htm.

  10. Altera Corp.: http://www.altera.com

  11. Triscend Inc.: http://www.triscend.com

  12. LucentWeb] http://www.lucentcom/micro/fpga/

  13. Hitachi Semiconductor: http://semiconductor.hitachi.com/news/triscend.html

  14. Peter Jung, Joerg Plechinger., “M-GOLD: a multimode basband platform for future mobile terminals”, CTMC’99, IEInternational Conference on Communications, Vancouver, June 1999.

    Google Scholar 

  15. Jan M. Rabaey: System Design at Universities: Experiences and Challenges;IEComputer Society International Conference on Microelectronic Systems Education (MSE’99), July 19-21, Arlington VA, USA

    Google Scholar 

  16. Pleiades Group: http://bwrc.eecs.berkeley.edu/Research/Configurable_Architectures/

  17. S. Copen Goldstein, H. Schmit, et al:“PipeRench: a Coprocessor for Streaming Multimedia Acceleration” in lSCA 1999. http://www.ece.cmu.edu/research/piperench/

  18. MIT Reinventing Computing: http://www.ai.mit.edu/projects/transitdpga_prototype_documents.html

  19. S. M. Sait, H. Youssef: Iterative Computer Algorithms with Applications in Engineering, IECS Press, USA, 1999

    MATH  Google Scholar 

  20. T. Lengauer: Combinatorical Algorithms for Integrated Circuit Layout, Wiley-Teibner, 1990

    Google Scholar 

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© 2001 Springer-Verlag Berlin Heidelberg

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Becker, J., Liebau, N., Pionteck, T., Glesner, M. (2001). Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_60

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  • DOI: https://doi.org/10.1007/3-540-44687-7_60

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-42499-4

  • Online ISBN: 978-3-540-44687-3

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