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X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor

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Field-Programmable Logic and Applications (FPL 2001)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2147))

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Abstract

This paper presents the full-duplex architecture of the X-MatchPRO lossless data compressor and its highly integrated implementation in a nonvolatile reprogrammable ProASIC FPGA. The X-MatchPRO architecture offers a data independent throughput of 100 Mbytes/s and simultaneous compression/decompression for a combine full-duplex performance of 200 Mbytes/s clocking at 25 MHz. Both compression and decompression channels fit into a single A500K130 ProASIC FPGA with a typical compression ratio that halves the original uncompressed data. The device is specially targeted to enhance the performance of Gbit/s data networks and storage applications where it can double the performance of the original system.

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© 2001 Springer-Verlag Berlin Heidelberg

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Núñez, J.L., Feregrino, C., Jones, S., Bateman, S. (2001). X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_65

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  • DOI: https://doi.org/10.1007/3-540-44687-7_65

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-42499-4

  • Online ISBN: 978-3-540-44687-3

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