Abstract
The speed at which a design could be tested (executed) really determines the use of FPGAs for rapid prototying. FPGAs provide reasonable routing resources, and a high capacity for mapping large hardware designs. However, profitable mapping of computations onto FPGAs is a complex task due to many tradeoffs involved. We present an approach to customize FPGA-based co-processors to most profitably execute loops to speed-up the the execution. Our framework specifically addresses the issues of parallelism, reducing data transfer overheads through reuse, and optimizing the safe frequency at which design can be maximally clocked.
This research was supported in part by DARPA award # ARMY DABT63-97-C-0029 and by NSF grant # CCR-0073512
Work done as a part of Masters’ thesis.
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© 2001 Springer-Verlag Berlin Heidelberg
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Subramanian, R., Pande, S. (2001). A Data Re-use Based Compiler Optimization for FPGAs. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_72
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DOI: https://doi.org/10.1007/3-540-44687-7_72
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