Abstract
A high-performance implementation of the International Data Encryption Algorithm (IDEA) is presented in this paper. The design was implemented in both bit-parallel and bit-serial architectures and a comparison of design tradeoffs using various measures is presented. On an Xilinx Virtex XCV300-6 FPGA, the bit-parallel implementation delivers an encryption rate of 1166 Mb/sec at a 82 MHz system clock rate, whereas the bit-serial implementation offers a 600 Mb/sec throughput at 150 MHz. Both designs are suitable for real-time applications, such as on-line high-speed networks. The implementation is runtime re-configurable such that key-scheduling is done by directly modifying the bitstream downloaded to the FPGA, hence enabling an implementation without the logic required for key-scheduling. Both implementations are scalable such that higher throughput is obtained with increased resource requirements. The estimated performances of the bit-parallel and bit-serial implementations on an XCV1000-6 device are 5.25 Gb/sec and 2.40 Gb/sec respectively.
Chapter PDF
Similar content being viewed by others
References
Annapolis Micro Systems, Inc. Wildcard Reference Manual, 1999. Revision 1.1.
Ascom. IDEACrypt Coprocessor Data Sheet, 1999. (http://www.ascom.ch/infosec/downloads/IDEACrypt_Coprocessor.pdf).
Ascom. IDEACrypt Kernel Data Sheet, 1999. (http://www.ascom.ch/infosec/downloads/IDEACrypt_Kernel.pdf).
H. Bonnenberg, A. Curiger, N. Felber, H. Kaeslin, and X. Lai. VLSI implementation of a new block cipher. In Proceedings of the IEEE International Conference on Computer Design: VLSI in Computer and Processors, pages 501–513, 1991.
J. Borst. Differential-linear cryptanalysis of IDEA. ESAT-COSIC Technical Report 96-2, Department of Electrical Engineering, Katholieke Universiteit Leuven, February 1997.
C. Carmichael. Virtex FPGA Series Configuration and Readback. Xilinx, Inc., September 1999. Application Note XAPP152, Version 1.2.
A. Curiger, H. Bonnenberg, R. Zimmerman, N. Felber, H. Kaeslin, and W. Fichtner. VINCI: VLSI implementation of the new secret-key block cipher IDEA. In Proceedings of the IEEE Custom Integrated Circuits Conference, pages 15.5.1–15.5.4, 1993.
A. V. Curiger, H. Bonnenberg, and H. Kaeslin. Regular VLSI architectures for multiplication modulo 2n + 1. IEEE Journal of Solid-State Circuits, 26(7):990–994, July 1991.
Electronic Frontier Foundation. DES challenge III broken in record 22 hours, January 1999. (http://www.eff.org/pub/Privacy/Crypto_misc/DESCracker/HTML/19990119deschallenge3.html).
M. George and P. Alfke. Linear Feedback Shift Registers in Virtex Devices. Xilinx, Inc., August 1999. Application Note XAPP210, Version 1.0.
S. C. Goldstein, H. Schmit, M. Budiu, M. Moe, and R. R. Taylor. PipeRench: A reconfigurable architecture and compiler. Computer, 33(4):70–77, April 2000.
R. Hartley and K. K. Parhi. Digit-Serial Computation. Kluwer Academic Publishers, 1995.
M. Hellman and S. Langford. Differential-linear cryptanalysis. In Advances in Cryptology, Proceedings of Eurocrypt 1994, pages 26–36, 1994.
S. Kelem. Virtex Configuration Architecture Advanced Users’ Guide. Xilinx, Inc., September 1999. Application Note XAPP151, Version 1.2.
L. R. Knudsen. Truncated and higher order differentials. In Proceedings of the Second International Workshop on Fast Software Encryption, pages 196–211, 1995.
X. Lai and J. Massay. A proposal for a new block encryption standard. In Advances in Cryptology, Proceedings of Eurocrypt 1990, pages 389–404, 1990.
X. Lai, J. Massay, and S. Murphy. Markov ciphers and differential cryptanalysis. In Advances in Cryptology, Proceedings of Eurocrypt 1991, pages 17–38, 1991.
M. P. Leong, O. Y. H. Cheung, K. H. Tsoi, and P. H. W. Leong. A bit-serial implementation of the international data encryption algorithm (IDEA). In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 122–131, April 2000.
P. H. W. Leong, M. P. Leong, O. Y. H. Cheung, T. Tung, C. M. Kwok, M. Y. Wong, and K. H. Lee. Pilchard-a reconfigurable computing platform with memory slot interface. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines (to appear), April 2001.
Helger Lipmaa. Idea: A cipher for multimedia architectures? In Selected Areas in Cryptography’ 98, pages 253–268, August 1998.
R.F. Lyon. Two’s complement pipeline multipliers. IEEE Transactions on Communications, 12:418–425, April 1976.
C. Meier and R. Zimmerman. A multiplier modulo (2n + 1). Diploma thesis, Institut für Integrierte Systeme, ETH, Zürich, Switzerland, February 1991.
O. Mencer, M. Morf, and M. J. Flynn. Hardware software tri-design of encryption for mobile communication units. In Proceedings of the IEEE International Conference on Acoustics, Speech and Signal Processing, volume 5, pages 3045–3048, May 1998.
C. Patterson. High performance DES encryption in Virtex FPGAs using JBits. In Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, pages 113–121, April 2000.
S. L. C. Salomao, V. C. Alves, and E. M. C. Filho. HiPCrypto: A high-performance VLSI cryptographic chip. In Proceedings of the Eleventh Annual IEEE ASIC Conference, pages 7–11, 1998.
B. Schneider. Applied Cryptography. John Wiley & Sons, second edition, 1996.
S. Wolter, H. Matz, A. Schubert, and R. Laur. On the VLSI implementation of the international data encryption algorithm IDEA. In Proceedings of the IEEE International Symposium on Circuits and Systems, volume 1, pages 397–400, 1995.
Xilinx. The Programmable Logic Data Book, 2000.
Xilinx, Inc. Xilinx Libraries Guide, 1999.
Xilinx, Inc. Xilinx Coregen Reference Guide, 2000. Version 3.1i.
R. Zimmermann, A. Curiger, H. Bonnenberg, H. Kaeslin, N. Felber, and W. Fichtner. A 177Mb/sec VLSI implementation of the international data encryption algorithm. IEEE Journal of Solid-State Circuits, 29(3):303–307, March 1994.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Cheung, O.Y.H., Tsoi, K.H., Leong, P.H.W., Leong, M.P. (2001). Tradeoffs in Parallel and Serial Implementations of the International Data Encryption Algorithm IDEA. In: Koç, Ç.K., Naccache, D., Paar, C. (eds) Cryptographic Hardware and Embedded Systems — CHES 2001. CHES 2001. Lecture Notes in Computer Science, vol 2162. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44709-1_28
Download citation
DOI: https://doi.org/10.1007/3-540-44709-1_28
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-42521-2
Online ISBN: 978-3-540-44709-2
eBook Packages: Springer Book Archive