Efficient Architecture for Exponentiation and Division in GF(2^m) Using Irreducible AOP

Abstract

The important arithmetic operations over finite fields include exponentiation, division, and inversion. An exponentiation operation can be implemented using a series of squaring and multiplication operations over GF(2^m) using a binary method, while division and inversion can be performed by the iterative application of an AB ² operation. Hence, it is important to develop a fast algorithm and efficient hardware for squaring, multiplication, and AB ² operations. The current paper presents new architectures for the simultaneous com-putation of multiplication and squaring operations, and the computation of an AB ² operation over GF(2^m) generated by an irreducible AOP of degree m. The proposed architectures offer a significant improvement in reducing the hardware complexity compared with previous architectures, and can also be used as a kernel circuit for exponentiation, division, and inversion architectures. Furthermore, since the proposed architectures include regularity, modularity and concurrency, they can be easily designed on VLSI hardware and used in IC cards.

This research was supported by University IT Research Center Project