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A Study on Insuring the Full Reliability of Finite State Machine

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Computational Science and Its Applications — ICCSA 2003 (ICCSA 2003)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2668))

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Abstract

In this paper, an efficient non-scan design-for-testability (DFT) method for finite state machine(FSM) is proposed. The proposed method always guarantees short test pattern generation time and complete fault efficiency. It has a lower area overhead than full-scan and other non-scan DFT methods and enables to apply test patterns at-speed. The efficiency of the proposed method is demonstrated using well-known MCNC’91 FSM benchmark circuits.

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References

  1. H. Fujiwara: Logic Testing and Design for Testability. The MIT Press (1985)

    Google Scholar 

  2. S. Bhattacharya, S. Dey: H-SCAN: A High Level Alternative to Full-Scan Testing With Reduced Area and Test Application Overheads. VLSI Test Symposium (1996) 74–80

    Google Scholar 

  3. B. Norwood, J. McCluskey: Orthogonal SCAN: Low Overhead SCAN for Data Paths. International Test Conference (1996) 659–668

    Google Scholar 

  4. S. Ohtake, H. Wada, T. Masuzawa, H. Fujiwara: A Non-scan DFT Method at Register-Transfer Level to Achieve Complete Fault Efficiency. ASP-Design Automation Conference (2000)

    Google Scholar 

  5. M. Abramovici, M. A. Breuer, A. D Friedman, Digital System Testing and Testable Design. Computer Science Press (1990)

    Google Scholar 

  6. P. C. Maxwell, R. C. Aitken, V. Johansen, I. Chiang: The Effect of Different Test Sets on Quality Level Prediction: When is 80% Better Than 90% ?. International Test Conference (1991) 358

    Google Scholar 

  7. Benoit Nadeau-Dostie: Design For At-speed Test, Diagnosis and Measurement. Kluwer Academic Publishers (2000)

    Google Scholar 

  8. V. Chickermane, E. Rudnick, P. Banerjee, J. H. Patel: Non-scan Design-For-Testability Techniques for Sequential Circuits. ACM/IEEE Design Automation Conference (1993) 236–241

    Google Scholar 

  9. S. Ohtake, T. Masuzawa, H. Fujiwara: A Non-scan DFT Method for Controllers to Achieve Complete Fault Efficiency,” Asian Test Symposium (1998) 204–211

    Google Scholar 

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Author information

Authors and Affiliations

  1. Department of Computing, Graduate School, Soongsil University, 1-1, Sangdo-5Dong, Dongjak-Ku, Seoul, Korea

    Sunwoong Yang, MoonJoon Kim & JaeHeung Park

  2. School of Computing, Soongsil University, 1-1, Sangdo-5Dong, Dongjak-Ku, Seoul, Korea

    Hoon Chang

Authors
  1. Sunwoong Yang
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  2. MoonJoon Kim
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  3. JaeHeung Park
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  4. Hoon Chang
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Editor information

Editors and Affiliations

  1. Army High Performance Computing Research Center, USA

    Vipin Kumar

  2. Department of Computer Science and Engineering, University of Minessota, MN, 55455, USA

    Vipin Kumar

  3. Department of Computer Science, University of Calgary, Calgary, AB, T2N1N4, Canada

    Marina L. Gavrilova

  4. Heuchera Technologies Inc., 122 9251-8 Yonge Street, Richmond Hill, ON, Canada, L4C 9T3

    Chih Jeng Kenneth Tan

  5. School of Computer Science, The Queen’s University of Belfast, Belfast, BT7 1NN, Northern Ireland, UK

    Chih Jeng Kenneth Tan

  6. Département d’informatique et de recherche opérationelle, Université de Montréal, Montréal, Québec, H3C 3J7, Canada

    Pierre L’Ecuyer

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© 2003 Springer-Verlag Berlin Heidelberg

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Yang, S., Kim, M., Park, J., Chang, H. (2003). A Study on Insuring the Full Reliability of Finite State Machine. In: Kumar, V., Gavrilova, M.L., Tan, C.J.K., L’Ecuyer, P. (eds) Computational Science and Its Applications — ICCSA 2003. ICCSA 2003. Lecture Notes in Computer Science, vol 2668. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44843-8_72

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  • DOI: https://doi.org/10.1007/3-540-44843-8_72

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-40161-2

  • Online ISBN: 978-3-540-44843-3

  • eBook Packages: Springer Book Archive

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