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A Compiler Framework for Tiling Imperfectly-Nested Loops

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Languages and Compilers for Parallel Computing (LCPC 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1863))

Abstract

This paper presents an integrated compiler framework for tiling a class of nontrivial imperfectly-nested loops such that cache locality is improved. We develop a new memory cost model to analyze data reuse in terms of both the cache and the TLB, based on which we compute the tile size with or without array duplication. We determine whether to duplicate arrays for tiling by comparing the respective exploited reuse factors. The preliminary results with several benchmark programs show that the transformed programs achieve a speedup of 1.09 to 3.82 over the original programs.

This work is sponsored in part by National Science Foundation through grants CCR-9975309, CCR-950254, MIP-9610379 and by Purdue Research Foundation.

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Author information

Authors and Affiliations

  1. Department of Computer Sciences, Purdue University, West Lafayette, IN 47907

    Yonghong Song & Zhiyuan Li

Authors
  1. Yonghong Song
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  2. Zhiyuan Li
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Editor information

Editors and Affiliations

  1. Department of Computer Science, University of California, San Diego, 9500 Gilman Drive, La Jolla, CA, 92093-0114, USA

    Larry Carter  & Jeanne Ferrante  & 

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© 2000 Springer-Verlag Berlin Heidelberg

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Song, Y., Li, Z. (2000). A Compiler Framework for Tiling Imperfectly-Nested Loops. In: Carter, L., Ferrante, J. (eds) Languages and Compilers for Parallel Computing. LCPC 1999. Lecture Notes in Computer Science, vol 1863. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44905-1_12

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  • DOI: https://doi.org/10.1007/3-540-44905-1_12

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67858-8

  • Online ISBN: 978-3-540-44905-8

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