Abstract
Astructural discipline for constructing speed-independent (hazard-free) circuits based on canonical chains of set-dominant and reset-dominant latches is proposed. The method can be applied to decompose complex asymmetric C-gate generated by logic synthesis from Signal Transition Graphs, and to map them into a restricted gate array ASIC library, such as IBM SA-12E that consists of logic gates with maximum four inputs and includes AO12, AOI12, OA12 and OAI12. The method is illustrated by new implementations of practically useful asynchronous circuits: a toggle element and an edge-triggered latch controller.
On leave from: Institute for Analytical Instrumentation, Russian Academy of Sci- ence, St. Petersburg, Russia; work in Newcastle supported by EPSRC GR/M94359.
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Starodoubtsev, N., Bystrov, A., Yakovlev, A. (2000). Semi-modular Latch Chains for Asynchronous Circuit Design. In: Soudris, D., Pirsch, P., Barke, E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45373-3_17
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