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Logarithmic Number System for Low-Power Arithmetic

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Integrated Circuit Design (PATMOS 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1918))

Abstract

In this paper, properties of the Logarithmic Number System (LNS) are investigated which can lead to power savings in a digital system. To quantitatively establish power savings, the equivalence of an LNS to a linear fixed-point system is, initially, explored and a related theorem is introduced. It is shown that LNS leads to reduction of the average bit assertion probability by more than 50%, in certain cases, over an equivalent linear representation. Finally, the impact of LNS on hardware architecture and, by means of that, to power dissipation, is discussed.

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References

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Author information

Authors and Affiliations

  1. Electrical and Computer Engineering Department, University of Patras, Greece

    V. Paliouras & T. Stouraitis

Authors
  1. V. Paliouras
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  2. T. Stouraitis
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Editor information

Editors and Affiliations

  1. Dept.of Electrical & Computer Engineering, Democritus University of Thrace, 67100, Xanthi, Greece

    Dimitrios Soudris

  2. Institute for Communication Theory and Signal Processing, University of Hanover, Appelstr.4, 30167, Hanover, Germany

    Peter Pirsch

  3. Institute for Microelectronic Systems, University of Hanover, Appelstr.4, 30167, Hanover, Germany

    Erich Barke

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© 2000 Springer-Verlag Berlin Heidelberg

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Paliouras, V., Stouraitis, T. (2000). Logarithmic Number System for Low-Power Arithmetic. In: Soudris, D., Pirsch, P., Barke, E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45373-3_30

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  • DOI: https://doi.org/10.1007/3-540-45373-3_30

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-41068-3

  • Online ISBN: 978-3-540-45373-4

  • eBook Packages: Springer Book Archive

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