Abstract
This paper presents an application where a self-timed approach reduces the switching noise in a mixed analog-digital circuit. Switching noise is of important concern in mixed signal systems, since it limits the performances of the analog part. Specifically, the digital core of an Analog to Digital converter has been designed following both a synchronous design style and another self-timed. Comparison between both versions shows the self-timed implementation reduce up to 50% the switching noise corresponding to the synchronous implementation.
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Allstot, D. J., Chee, S-H. and Shrivastawa, M.: Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal ICs. IEEE Transactions on Circuits and Systems I, vol 40, pp 553–563, Sept. 1993.
Ng, H-T. and Allstot, D. J.: CMOS Current Steering Logic for Low-Voltage Mixed-Signal Integrated Circuit. IEEE Trans. on VLSI Systems, Vol. 5, pp 301–308, Sept. 1997.
Tsividis, Y.: Mixed Analog-Digital VLSI Design and Technology. McGraw-Hill, 1995.
Albuquerque, E., Fernandes, J. and Silva, M.: NMOS current-balanced logic. Electronics Letters, vol 32, pp 997–998, May 1996.
Jiménez, R., Acosta, A.J., Juan, J., Bellido, M.J. and Valencia, M.: Study and Analysis of Low-Voltage/Low-Power CMOS Logic Families for Low Switching Noise. Proc. of 9th Int. Workshop Power and Timing Modeling, Optimization and Simulation (PATMOS’99), pp. 377–386, Kos Island, October 1999.
Gonzalez, J.L. and Rubio, A.: Low Switching Noise CMOS Circuit Design Strategy based on Regular Self-Timed Structures. Proc. Midwest Symposium on Circuits and Systems, pp. 176–179, 1999.
Jiménez, R., Acosta, A.J., Barriga, A., Bellido, M.J. and Valencia, M.: Efficient Self-Timed Circuits based on weak NMOS-Trees. Proc. of 5th IEEE Int. Conference on Electronics, Circuits and Systems (ICECS’98), pp. 179–182, Vol. 3, Lisboa, September 1998.
Peralias, E, Rueda, A. and Huertas, J.L.: A DFT Technique for Analog-to-Digital Converters with Digital Correction. Proc. 15th IEEE VLSI Test Symposium (VTS’97), pp. 302–307, 1997.
Peralias, E.J., Acosta, A.J., Rueda, A. and Huertas, J.L.: A VHDL-based Methodology for Design and Verification of Pipeline A/D Converters. Proc. Design, Automation and Test in Europe (DATE’00), pp. 534–538, March 2000.
Berkel, K.v., Burgess, R., Kessels, M., Schalij, F. and Peeters, A.: Asynchronous Circuits for Low Power: A DCC Error Corrector. IEEE Design and Test of Computers, Vol. 11, no. 2, pp. 22–32, Summer 1994.
Jiménez, R.: Una aportación al Diseño de Circuitos Integrados CMOS Autotemporizados. PhD. Thesis, Universidad de Sevilla, Julio 2000 (in Spanish).
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Jiménez, R., Acosta, A.J., Peralías, E.J., Rueda, A. (2000). An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits. In: Soudris, D., Pirsch, P., Barke, E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45373-3_31
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DOI: https://doi.org/10.1007/3-540-45373-3_31
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