Abstract
We prove an analogue of Brent’s lemma for BSP-like parallel machines featuring a hierarchical structure for both the interconnection and the memory. Specifically, for these machines we present a uniform scheme to simulate any computation designed for v processors on a v′-processor configuration with v′ ≤ v and the same overall memory size. For a wide class of computations the simulation exhibits optimal O (v/v′) slowdown. The simulation strategy aims at translating communication locality into temporal locality. As an important special case (v′= 1), our simulation can be employed to obtain efficient hierarchy-conscious sequential algorithms from efficient fine-grained ones.
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Fantozzi, C., Pietracaprina, A., Pucci, G. (2002). Seamless Integration of Parallelism and Memory Hierarchy. In: Widmayer, P., Eidenbenz, S., Triguero, F., Morales, R., Conejo, R., Hennessy, M. (eds) Automata, Languages and Programming. ICALP 2002. Lecture Notes in Computer Science, vol 2380. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45465-9_73
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DOI: https://doi.org/10.1007/3-540-45465-9_73
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