Abstract
Various approaches to buffer size and management for output buffering in ATM switches supporting delay sensitive traffic are reviewed. Discrete worst case arrival and service functions are presented. Using this format, bounds are developed for buffer size under zero cell loss for leaky bucket constrained sources. Tight bounds are developed for the case of discrete arrival functions with fluid servers and fluid arrival functions with discrete servers. A bound on the buffer size is also proposed for the case of discrete arrival and service process. While this bound is not exact, the maximum gain that could be achieved by a tighter bound is bounded. In some cases it is possible to reduce the buffer size requirements through over allocation of link bandwidth. Feasibility conditions for this scenario are developed.
Chapter PDF
Similar content being viewed by others
References
Agrawal, R., R. Cruz, C. Okino, R. Rajan, “Performance Bounds for Flow Control Protocols”, IEEE/ACM Transactions on Networking, Vol.7,No.3, June 1999.
Chang, C-S, “On Deterministic Traffic Regulation and Service Guarantees: A Systematic Approach by Filtering”, IEEE Transactions on Information Theory, Vol. 44, No. 3, May 1998, pp1097–1110.
Elwalid, A., D. Mitra, R.H. Wentworth, “A New Approach for Allocating Buffers and Bandwidth to Heterogeneous Regulated Traffic in an ATM Node”, IEEE Journal on Selected Areas in Communications, Vol 13, No. 6, August 1995, pp 1115–1127.
Garg, R., X. Chen, “RRR: Recursive Round Robin Scheduler”, IEEE Globecom’98, paper S94–4, November 1998.
Guerin, R., S. Kamat, V. Peris, R. Rajan, “Scalable QoS Provision through Buffer Management”, Computer Communications Review, Vol. 28, No. 4, 1998
Katevenis, M., S. Sidiropoulos, C. Courcoubetis, “Weighted Round Robin cell Multiplexing in a General Purpose ATM Switch Chip”, IEEE Journal on Selected Areas in Communications, Vol. 9, No. 8, October 1991.
LeBoudec, J-Y, “Application of Network Calculus to Guaranteed Service Networks”, IEEE Transactions on Information Theory, Vol. 44, No. 3, May 1998, pp1087–1096
LoPresti, F., Z-L. Zhang, J. Kurose, D. Towsley, “Source Timescale and Optimal Buffer/Bandwidth Tradeoff for Regulated Traffic in an ATM Node”, Proceedings of IEEE INFOCOM’97.
Sasaki, G., “Input Buffer Requirements for Round Robin Polling Systems”, Performance Evaluation, Vol. 18, 1993, pp 237–261.
Stiliadis, D., A. Varma, “Latency-Rate Servers: A General Model for Analysis of Traffic Scheduling Algorithms”, IEEE Infocom’96, San Francisco, March 1996, pp 111–119.
Wright, S., Y. Viniotis, “Simulation Study of Maximal Delays in Various Link Scheduling Algorithms”, IEEE Globecom’98, paper S117–7, November 1998.
Wright, S., “Delay Bounds and Connection Admission Control for Burstiness-Class Queuing”, Ph.D. Thesis, North Carolina State University, 1999.
Wright, S., Y. Viniotis, “ATM Network Procedures Supporting Delay QoS”, IEEE/IEICE ATM Workshop 99, Kochi City, Kochi, Japan May 24–27, 1999.
Wright, S., Y. Viniotis, “Burstiness-Class Based Queueing in ATM Networks Supporting Delay QoS Bounds”, IEEE Infocom 2000, Tel Aviv, Israel, March 2000.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Wright, S., Viniotis, Y. (2000). Buffer Size Requirements for Delay Sensitive Traffic Considering Discrete Effects and Service-Latency in ATM Switches. In: Pujolle, G., Perros, H., Fdida, S., Körner, U., Stavrakakis, I. (eds) Networking 2000 Broadband Communications, High Performance Networking, and Performance of Communication Networks. NETWORKING 2000. Lecture Notes in Computer Science, vol 1815. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45551-5_6
Download citation
DOI: https://doi.org/10.1007/3-540-45551-5_6
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-67506-8
Online ISBN: 978-3-540-45551-6
eBook Packages: Springer Book Archive