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A Reconfigurable Content Addressable Memory

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Parallel and Distributed Processing (IPDPS 2000)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1800))

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Abstract

Content Addressable Memories or CAMs are popular parallel matching circuits. They provide the capability, in hardware, to search a table of data for a matching entry. This functionality is a high performance alternative to popular software-based searching schemes. CAMs are typically found in embedded circuitry where fast matching is essential. This paper presents a novel approach to CAM implementation using FPGAs and run-time reconfiguration. This approach produces CAM circuits that are smaller, faster and more flexible than traditional approaches.

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References

  1. Steven A. Guccione and Delon Levi. XBI: A Java-based interface to FPGA hardware. In John Schewel, editor, Configurable Computing Technology and its use in High Performance Computing, DSP and Systems Engineering, Proc. SPIE Photonics East, pages 97–102, Bellingham, WA, November 1998. SPIE — The International Society for Optical Engineering.

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Author information

Authors and Affiliations

  1. Xilinx Inc., 2100 Logic Drive, San Jose, CA, 95124, USA

    Steven A. Guccione, Delon Levi & Daniel Downs

Authors
  1. Steven A. Guccione
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  2. Delon Levi
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  3. Daniel Downs
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Editor information

Editors and Affiliations

  1. Centre Universitaire d’Informatique, Université de Genève, 24, rue Général Dufour, CH-1211, Genève 4, Switzerland

    José Rolim

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© 2000 Springer-Verlag Berlin Heidelberg

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Guccione, S.A., Levi, D., Downs, D. (2000). A Reconfigurable Content Addressable Memory. In: Rolim, J. (eds) Parallel and Distributed Processing. IPDPS 2000. Lecture Notes in Computer Science, vol 1800. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45591-4_122

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  • DOI: https://doi.org/10.1007/3-540-45591-4_122

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67442-9

  • Online ISBN: 978-3-540-45591-2

  • eBook Packages: Springer Book Archive

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