Abstract
Digital hardware is treated as a collection of interacting parallel components. The Aniseed method (Analysis In SDL Enhancing Electronic Design) uses SDL (Specification and Description Language) to specify and analyse timing characteristics of hardware designs. A library contains specifications of typical components in single/multi-bit and untimed/timed forms. Timing may be specified at an abstract, behavioural or structural level. Consistency of temporal and functional aspects may be assessed between designs at different levels of detail. Timing characteristics of a design may also be inferred from validator traces.
This is a preview of subscription content, log in via an institution.
Buying options
Tax calculation will be finalised at checkout
Purchases are for personal use only
Learn about institutional subscriptionsPreview
Unable to display preview. Download preview PDF.
References
F. J. Argul Marin and K. J. Turner. Extending hardware description in SDL. Technical Report CSM-155, Department of Computing Science and Mathematics, University of Stirling, UK, Feb. 2000.
I. S. Bonatti and R. J. O. Figueiredo. An algorithm for the translation of SDL into synthesizable VHDL. Current Issues In Electronic Modeling, 3, Aug. 1995.
E. Bounimova, V. Levin, O. Başbuğoğlu, and K. İnan. A verification engine for SDL specification of communication protocols. In S. Bilgen, M. U. Çağlayan, and C. Ersoy, editors, Proc. 1st. Symposium on Computer Networks, pages 16–25, Istanbul, Turkey, 1996.
G. Csopaki and K. J. Turner. Modelling digital logic in SDL. In T. Mizuno, N. Shiratori, T. Higashino, and A. Togashi, editors, Proc. Formal Description Techniques X/Protocol Specification, Testing and Verification XVII, pages 367–382. Chapman-Hall, London, UK, Nov. 1997.
J.-M. Daveau, G. F. Marchioro, C. A. Valderrama, and A. A. Jerraya. VHDL generation from SDL specifications. In C. Delgado-Kloos and E. Cerny, editors, Proc. Computer Hardware Description Languages and their Applications XIII, pages 20–25. Chapman-Hall, London, UK, Apr. 1997.
T. Hadlich and T. Szczepanski. The ODE system — An SDL based approach to hardware-software co-design. In C. Müller-Schlör, F. Geerinckx, B. Stanford-Smith, and R. van Riet, editors, Embedded Microprocessor Systems, pages 269–281. IOS Press, Amsterdam, Netherlands, 1996.
G. J. Holzmann. Practical methods for the formal validation of SDL. Computer Communications, 15(2):129–134, 1992.
ITU. Message Sequence Chart (MSC). ITU-T Z.120. International Telecommunications Union, Geneva, Switzerland, 1996.
ITU. Specification and Description Language. ITU-T Z.100. International Telecommunications Union, Geneva, Switzerland, 1996.
J. Staunstrup and T. Kropf. IFIP WG10.5 benchmark circuits. http://goethe.ira.uka.de/hvg/benchmarks.html, July 1996.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Turner, K.J., Argul-Marin, F.J., Laing, S.D. (2000). Concurrent Specification And Timing Analysis of Digital Hardware using SDL. In: Rolim, J. (eds) Parallel and Distributed Processing. IPDPS 2000. Lecture Notes in Computer Science, vol 1800. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45591-4_137
Download citation
DOI: https://doi.org/10.1007/3-540-45591-4_137
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-67442-9
Online ISBN: 978-3-540-45591-2
eBook Packages: Springer Book Archive