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Timing Analysis of Assembler Code Control-Flow Paths

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FME 2002:Formal Methods—Getting IT Right (FME 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2391))

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Abstract

Timing analysis of assembler code is essential to achieve the strongest possible guarantee of correctness for safety-critical, real-time software. Previous work has shown how timing constraints on control-flow paths through high-level language programs can be formalised using the semantics of the statements comprising the path. We extend these results to assembler-level code where it becomes possible to not only determine timing constraints, but also to verify them against the known execution times for each instruction. A minimal formal model is developed with both a weakest liberal precondition and a strongest postcondition semantics. However, despite the formalism’s simplicity, it is shown that complex timing behaviour associated with instruction pipelining and iterative code can be modelled accurately.

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Author information

Authors and Affiliations

  1. Software Verification Research Centre, The University of Queensland, Australia

    C. J. Fidge

Authors
  1. C. J. Fidge
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Editor information

Editors and Affiliations

  1. Department of Information Technology, Uppsala University, P.O. Box 337, 751 05, Uppsala, Sweden

    Lars-Henrik Eriksson

  2. Software Verification Research Centre, The University of Queensland, Queensland, 4072, Australia

    Peter Alexander Lindsay

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© 2002 Springer-Verlag Berlin Heidelberg

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Fidge, C.J. (2002). Timing Analysis of Assembler Code Control-Flow Paths. In: Eriksson, LH., Lindsay, P.A. (eds) FME 2002:Formal Methods—Getting IT Right. FME 2002. Lecture Notes in Computer Science, vol 2391. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45614-7_21

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  • DOI: https://doi.org/10.1007/3-540-45614-7_21

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-43928-8

  • Online ISBN: 978-3-540-45614-8

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