Abstract
Recently, an embedding of the synchronous programming language Quartz (an Esterel variant) in the theorem prover HOL has been presented. This embedding is based on control flow predicates that refer to macrosteps of the programs. The original semantics of synchronous languages like Esterel is however normally given at the more detailed microstep level. This paper describes how a variant of the Esterel microstep semantics has been defined in HOL and how its equivalence to the control flow predicate semantics has been proved. Beneath proving the equivalence of the micro- and macrostep semantics, the work presented here is also an important extension of the existing embedding: While reasoning at the microstep level is not necessary for code generation, it is sometimes advantageous for understanding programs, as some effects like schizophrenia or causality problems become only visible at the microstep level.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
L. Aceto, B. Bloom, and F. Vaandrager. Turning SOS rules into equations. Information and Computation, 111:1–52, 1994.
L. Aceto, W. Fokkink, and C. Verhoef. Structural operational semantics. In J. Bergstra, A. Ponse, and S. Smolka, editors, Handbook of Process Algebra, pages 197–292. Elsevier, Amsterdam, 2001.
C. Angelo, L. Claesen, and H. D. Man. Degrees of Formality in Shallow Embedding Hardware Description Languages in HOL. In J. Joyce and C.-J. Seger, editors, Higher Order Logic Theorem Proving and Its Applications, volume 780 of LNCS, pages 87–99, Vancouver, Canada, August 1993. University of British Columbia, Springer-Verlag, published 1994.
G. Berry. A hardware implementation of pure Esterel. In ACM International Workshop on Formal Methods in VLSI Design, Miami, Florida, January 1991.
G. Berry. The foundations of Esterel. In G. Plotkin, C. Stirling, and M. Tofte, editors, Proof, Language and Interaction: Essays in Honour of Robin Milner. MIT Press, 1998.
G. Berry. The constructive semantics of pure Esterel, July 1999.
G. Berry. The Esterel v5_91 language primer. http://www.esterel.org, June 2000.
G. Berry and G. Gonthier. The Esterel synchronous programming language: Design, semantics, implementation. Science of Computer Programming, 19(2):87–152, 1992.
R. Boulton. A HOL semantics for a subset of ELLA. technical report 254, University of Cambridge, Computer Laboratory, April 1992.
R. Boulton, A. Gordon, M. Gordon, J. Herbert, and J. van Tassel. Experience with embedding hardware description languages in HOL. In International Conference on Theorem Provers in Circuit Design (TPCD), pages 129–156, Nijmegen, June 1992. IFIP TC10/WG 10.2, North-Holland.
F. Boussinot. SugarCubes implementation of causality. Research Report 3487, Institut National de Recherche en Informatique et en Automatique (INRIA), Sophia Antipolis Cedex (France), September 1998.
J. Brzozowski and C.-J. Seger. Asynchronous Circuits. Springer Verlag, 1995.
N. Day and J. Joyce. The semantics of statecharts in HOL. In J. Joyce and C.-J. Seger, editors, Higher Order Logic Theorem Proving and its Applications, volume 780 of LNCS, pages 338–352, Vancouver, Canada, August 1993. University of British Columbia, Springer-Verlag, published 1994.
Esterel-Technology. Website. http://www.esterel-technologies.com.
A. Girault and G. Berry. Circuit generation and verification of Esterel programs. Research report 3582, INRIA, December 1998.
M. Gordon and T. Melham. Introduction to HOL: A Theorem Proving Environment for Higher Order Logic. Cambridge University Press, 1993.
N. Halbwachs and F. Maraninchi. On the symbolic analysis of combinational loops in circuits and synchronous programs. In Euromicro Conference, Como, Italy, September 1995.
Jester Home Page. Website. http://www.parades.rm.cnr.it/projects/jester/jester.html.
L. Lavagno and E. Sentovich. ECL: A specification environment for system-level design. In ACM/IEEE Design Automation Conference (DAC), 1999.
G. Logothetis and K. Schneider. Extending synchronous languages for generating abstract real-time models. In European Conference on Design, Automation and Test in Europe (DATE), Paris, France, March 2002. IEEE Computer Society.
S. Malik. Analysis of cycle combinational circuits. IEEE Transactions on Computer Aided Design, 13(7):950–956, July 1994.
T. Melham. Automating recursive type definitions in higher order logic. Technical Report 146, University of Cambridge Computer Laboratory, Cambridge CB2 3QG, England, September 1988.
G. Plotkin. A Structural Approach to Operational Semantics. Technical Report FN-19, DAIMI, Aarhus University, 1981.
A. Poigné and L. Holenderski. Boolean automata for implementing pure Esterel. Arbeitspapiere 964, GMD, Sankt Augustin, 1995.
POLIS Homepage. Website. http://www-cad.eecs.berkeley.edu/.
R. Reetz. Deep Embedding VHDL. In E. Schubert, P. Windley, and J. Alves-Foss, editors, Higher Order Logic Theorem Proving and its Applications, volume 971 of LNCS, pages 277–292, Aspen Grove, Utah, USA, September 1995. Springer-Verlag.
F. Rocheteau and N. Halbwachs. Pollux, a Lustre-based hardware design environment. In P. Quinton and Y. Robert, editors, Conference on Algorithms and Parallel VLSI Architectures II, Chateau de Bonas, 1991.
K. Schneider. A verified hardware synthesis for Esterel. In F. Rammig, editor, International IFIP Workshop on Distributed and Parallel Embedded Systems, pages 205–214, Schloß Ehringerfeld, Germany, 2000. Kluwer Academic Publishers.
K. Schneider. Embedding imperative synchronous languages in interactive theorem provers. In International Conference on Application of Concurrency to System Design (ICACSD 2001), pages 143–156, Newcastle upon Tyne, UK, June 2001. IEEE Computer Society Press.
K. Schneider and M. Wenz. A new method for compiling schizophrenic synchronous programs. In International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), pages 49–58, Atlanta, USA, November 2001. ACM.
T. Shiple, G. Berry, and H. Touati. Constructive analysis of cyclic circuits. In European Design and Test Conference (EDTC), Paris, France, 1996. IEEE Computer Society Press.
S. Tini. Structural Operational Semantics for Synchronous Languages. PhD thesis, University of Pisa, 2000.
C. Zhang, R. Shaw, R. Olsson, K. Levitt, M. Archer, M. Heckman, and G. Benson. Mechanizing a programming logic for the concurrent programming language microSR in HOL. In J. Joyce and C.-J. Seger, editors, Higher Order Logic Theorem Proving and its Applications, volume 780 of LNCS, pages 29–43, Vancouver, Canada, August 1993. University of British Columbia, Springer-Verlag, published 1994.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Schneider, K. (2002). Proving the Equivalence of Microstep and Macrostep Semantics. In: Carreño, V.A., Muñoz, C.A., Tahar, S. (eds) Theorem Proving in Higher Order Logics. TPHOLs 2002. Lecture Notes in Computer Science, vol 2410. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45685-6_21
Download citation
DOI: https://doi.org/10.1007/3-540-45685-6_21
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-44039-0
Online ISBN: 978-3-540-45685-8
eBook Packages: Springer Book Archive