Abstract
The technology and application trends leading to current day multiprocessor architectures such as chip multiprocessors, embedded architectures, and massively parallel architectures, demand faster, more efficient, and more scalable cache coherence schemes than the existing ones. In this paper we present a new scheme that has a potential to meet such a demand. The software support for our scheme is in the form of program annotations to detect shared accesses as well as release synchronizations that represent data sharing boundaries. A small hardware called Coherence Buffer (CB) with an associated controller, local to each processor forms the control unit to locally enforce cache coherence actions which are off the critical path. Our simulation study shows that a 8 entry 4-way associative CB helps achieve a speedup of 1.07 - 4.31 over full-map 3-hop directory scheme for five of the SPLASH-2 benchmarks (representative of migratory sharing, producer-consumer and write-many workloads), under Release Consistency model. B. Monien and R. Feldmann (Eds.): Euro-Par 2002, LNCS 2400, pp. 543-546.
Chapter PDF
Similar content being viewed by others
Keywords
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.
References
D. J. Lilja. Cache Coherence in Large-Scale Shared-Memory Multiprocessors: Issues and Comparisons. ACM Computing Surveys, 3(25):303–338, September 1993.
H. Sarojadevi, S.K. Nandy, and S. Balakrishnan. Coherence Buffer: An Architectural Support for Maintaining Early Cache Coherence at Data Sharing Boundaries. Technical report, CAD Lab, IISc, http://www.serc.iisc.ernet.in/~nandy, May 2002.
A.C. Lai and Babak Falsafi. Selective, Accurate, and Timely self-invalidation Using Last-Touch Prediction. In Proceedings of the ISCA, June 2000.
A. R. Lebeck and D. A. Wood. Dynamic self-invalidation: Reducing coherence overhead in Shared-memory multiprocessors. In Proceedings of the ISCA, pages 48–59, May 1995.
M. D. Hill, J. L. Larus, S. K. Reinhardt, and D. A. Wood. Cooperative Shared Memory: Software and Hardware for Scalable Multiprocessors. In Proceedings of the ASPLOS, pages 262–273, June 1992.
F. Dahlgren and P. Stenström. Using Write Caches to Improve Performance of Cache Coherence Protocols in Shared-Memory Multiprocessors. Journal of Parallel and Distributed Computing, pages 193–210, April 1995.
S.K. Nandy and Ranjani Narayan. An Incessantly Coherent Cache Scheme for Shared Memory Multithreaded Systems. Technical Report LCS, CSG-Memo 356, Massachusetts Institute of Technology, September 1994.
C. J. Hughes, V. S. Pai, P. Ranganathan, and S. V. Adve. Rsim: Simulating Shared-Memory Multiprocessors with ILP Processors. IEEE Computer, 35(2):40–49, February 2002.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Sarojadevi, H., Nandy, S.K., Balakrishnan, S. (2002). Enforcing Cache Coherence at Data Sharing Boundaries without Global Control: A Hardware-Software Approach. In: Monien, B., Feldmann, R. (eds) Euro-Par 2002 Parallel Processing. Euro-Par 2002. Lecture Notes in Computer Science, vol 2400. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45706-2_73
Download citation
DOI: https://doi.org/10.1007/3-540-45706-2_73
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-44049-9
Online ISBN: 978-3-540-45706-0
eBook Packages: Springer Book Archive