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Resonant Multistage Charging of Dominant Capacitances

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Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2451))

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Abstract

It has been shown [2] that adiabatic switching can significantly reduce the dynamic power dissipation in an integrated circuit. Due to the overhead in the realization of adiabatic logic blocks [3] the best results are achieved when it is used only for charging dominant loads in an integrated circuit [7]. It has been demonstrated [4] that a multi stage driver is needed for minimal power dissipation. In this article a complete three stage driver including the generation of oscillating supply is described. To obtain a minimal power dissipation during synchronization the resonant frequency has to be constant. Therefore the waveforms for the logic states of the signal and the realization of a single stage differ from those presented in [4]. In the H-SPICE simulations losses of the inductor are taken into account. This allows to estimate the power reduction that is achievable in a real system.

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References

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© 2002 Springer-Verlag Berlin Heidelberg

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Saas, C., Nossek, J.A. (2002). Resonant Multistage Charging of Dominant Capacitances. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_11

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  • DOI: https://doi.org/10.1007/3-540-45716-X_11

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-44143-4

  • Online ISBN: 978-3-540-45716-9

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