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Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library

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Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation (PATMOS 2002)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2451))

Abstract

Adiabatic circuits are usually designed with methodologies optimized for the application in which they are used. In this work we show how a conventional design-flow based on an adiabatic standard-cell library and semiautomatic tools allow the quick and easy design and verification of a complex adiabatic system, without loosing the energy reduction benefits. The methodology has been applied to the design of positive feedback adiabatic logic (PFAL) carry look-ahead adders (CLA). Post-layout simulations of the standard-cell PFAL CLAs show a 94% energy recovery as compared to a conventional static CMOS CLA at 10 MHz, and 86% at 100 MHz. The standard-cell PFAL CLAs are also more energy efficient or comparable than other custom adiabatic CLAs found in the literature.

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Authors and Affiliations

  1. Dipartimento di Ingegneria dell’Informazione: Elettronica, Informatica, Telecomunicazioni, University of Pisa, Via Diotisalvi 2, I-56122, Pisa, Italy

    Antonio Blotti, Maurizio Castellucci & Roberto Saletti

Authors
  1. Antonio Blotti
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  2. Maurizio Castellucci
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  3. Roberto Saletti
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Editor information

Editors and Affiliations

  1. Ecole d’Ingénieurs du Canton de Vaud Microelectronics and Systems Institute, Digital Communications Team, Swiss University of Applied Science, Rue de Galilée 15, 1400, Yverdon, Switzerland

    Bertrand Hochet

  2. Instituto de Microelectrónica de Sevilla-CNM-CSIC Departamento do Diseño Digital Departamento de Electrónica y Electromagnetismo Departamento de Tecnología Electrónica, Universidad de Sevilla, Avda. Reina Mercedes, s/n. Edif. CICA

    Antonio J. Acosta  & Manuel J. Bellido  & 

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© 2002 Springer-Verlag Berlin Heidelberg

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Blotti, A., Castellucci, M., Saletti, R. (2002). Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_13

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  • DOI: https://doi.org/10.1007/3-540-45716-X_13

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-44143-4

  • Online ISBN: 978-3-540-45716-9

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