Abstract
Adiabatic circuits are usually designed with methodologies optimized for the application in which they are used. In this work we show how a conventional design-flow based on an adiabatic standard-cell library and semiautomatic tools allow the quick and easy design and verification of a complex adiabatic system, without loosing the energy reduction benefits. The methodology has been applied to the design of positive feedback adiabatic logic (PFAL) carry look-ahead adders (CLA). Post-layout simulations of the standard-cell PFAL CLAs show a 94% energy recovery as compared to a conventional static CMOS CLA at 10 MHz, and 86% at 100 MHz. The standard-cell PFAL CLAs are also more energy efficient or comparable than other custom adiabatic CLAs found in the literature.
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Blotti, A., Castellucci, M., Saletti, R. (2002). Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_13
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DOI: https://doi.org/10.1007/3-540-45716-X_13
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