Abstract
Clock distribution networks appear to be a.ected by combination of thermally and electrically related issues. A new methodology is presented in this paper that produces optimized sizes for critical wires, combining thermal and electrical analysis. In particular, its application to a clock network is reported, to show alleviation strategies to undesired Deep Submicron (DSM) effects.
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Casu, M.R., Graziano, M., Masera, G., Piccinini, G., Prono, M.M., Zamboni, M. (2002). Clock Distribution Network Optimization under Self-Heating and Timing Constraints. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_20
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DOI: https://doi.org/10.1007/3-540-45716-X_20
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