Abstract
This paper uses a analytical-based characterization model to discuss energy consumption of register files with different circuit techniques that using multi-port SRAM technology. Energy distribution chart of register file with different architectural parameters is acquired according to the calculation results of energy model. How the decoder structure and the dominant component have effect on the power of the register file is demonstrated with emphasise. With this low power method, a 64×32 bits three-port register file operate at a 500MHz frequency with 54mW power dissipation.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Ikeda, Makoto; Asada, Kunihiro, Data bypassing register file for low power microprocessor. IEICE Transactions on Electronics E78-C 10 Oct 1995 Inst of Electronics, Inf & Commun Engineers of Japan p 1470–1472
Joshi, R.V.; Hwang, W.; Wilson, S.; Shahidi, G.; Chuang, C.T, Low power 900 MHz register file (8 ports, 32 words × 64 bits) IN 1.8 v, 0.25μm SOI technology. Proceedings of the IEEE International Conference on VLSI Design Jan 3–Jan 7 2000 2000 p 44–49
R. Y. Chen, R. M. Owens, M. J. Irwin, and R. S. Bajwa, Validation of an architectural level power analysis technique. In DAC’98, San Francisco, CA, June 1998.
Veendrick, H.J.M. et al, Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits, IEEE JSSC, vol. SC-19, no. 4, pp. 468–473, August 1984.
Zyuban, V.; Kogge, P. The energy complexity of register files, Low Power Electronics and Design, 1998. Proceedings. 1998 International Symposium on, 1998 Page(s): 305–310
Wilton, S. E., and Jouppi, N., An enhanced access and cycle time model for on-chipcaches. DEC WRL Research Report 93/5, July 1994
H. Nambu, A 1.8ns Access, 550MHz 4.5Mb CMOS SRAM. in proc. 1998 ISSCC, pp. 360–361.
T. Suzuki et. al., Synonym hit ram: A 500MHz 1.5ns CMOS SRAM Macro with 576b parallel comparison and parity check functions. In: 1998IEEE international solid-state circuits conference, pp. 348–349, January 1995.
R. Franch et. al., 640-ps, 0.25•m CMOS 16×64-b Three-port Register File. IEEE JSSC, vol.32, No.8, Auguest 1997.
S. Chao et. al., A 1.3ns 32×32 three port BiCMOS register file. in proc. 1994 BCTM, 1994, pp.91–94.
M. Nomura et. al., A 500-MHz, 0.4•m CMOS 32×32 3-port Register File. in proc. 1995 CICC, pp. 151–154.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Xue-mei, Z., Yi-zheng, Y. (2002). Design and Realization of a Low Power Register File Using Energy Model. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_27
Download citation
DOI: https://doi.org/10.1007/3-540-45716-X_27
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-44143-4
Online ISBN: 978-3-540-45716-9
eBook Packages: Springer Book Archive