Abstract
The objective of this paper is to explore the applicability of clock gating techniques to binary counters in order to reduce the power consumption as well as the switching noise generation. A measurement methodology to establish right comparisons between different implementations of gate- clocked counters is presented. Basically two ways of applying clock gating are considered: clock gating on independent bits and clock gating on groups of bits. The right selection of bits where clock gating must be applied and the suited composition of groups of bits is essential when applying this technique. We have found groupment of bits is the best option when applying clock gating to reduce power consumption and specially to reduce noise generation.
This work has been sponsored by the Spanish MCYT TIC2000-1350 MODEL and TIC2001- 2283 VERDI Projects
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References
Benini, L., De Micheli, G., “Automatic Synthesis of Low Power Gated-Clock Finite-State Machines”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol.15, no. 6, June 1996., pp. 630–643
Benini, L., DeMicheli, G., Macii, E., Poncino, M. y Scarsi, R. “Symbolic Synthesis of Clock-Gating Logic for Power Optimization of Control-Oriented Synchronous Networks”. European Design & Test Conference (EDTC-97), pp. 514–520.
Piguet, C., “Low-Power Design of Finite State Machines”, in PATMOS, pp. 25–34, Bologna, Sept. 1996.
A. J. Acosta, R. Jiménez, J., M. J. Juan, Bellido, and M. Valencia, “Influence of clocking strategies on the design of low switching-noise digital and mixed-signal VLSI circuits”, in 10th PATMOS, pp. 316–326, Göttingen, Sept. 2000.
Emnett, F., Biegel, M., “Power Reduction through RTL Clock Gating”. SNUG San Jose 2000.
Stojanovic, V., OKlobdzija, V.G., “Comparative Analysis of Master-Slave LAtches and Flip-Flops for High-Performance and Low-Power Sistems”, IEEE Journal of Solid State Circuits, Vol. 34, No. 4, April 1999.
Jiménez, R., Parra, P., Sanmartín, P. and Acosta, A.J.: “Analysis of high-performance flip-flops for submicron mixed-signal applications”, International Journal of Analog Integrated Circuits and Signal Processing. Kluwer Academic Publishers. (accepted)
X. Aragonès, J. L. González and A. Rubio, “Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs”. Kluwer Academic Publishers, 1999.
Stan, M., Tenca, A. and Ercegovac, M., “Long and Fast Up/Down Counters”. IEEE Transactions on Computers, Vol. 47, No. 7, July 1998.
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Parra, P., Acosta, A., Valencia, M. (2002). Selective Clock-Gating for Low Power/Low Noise Synchronous Counters. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_45
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DOI: https://doi.org/10.1007/3-540-45716-X_45
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