Skip to main content
SpringerLink
Log in

Processor Architectures for Multimedia Applications

  • Chapter
  • First Online:
Embedded Processor Design Challenges (SAMOS 2001)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2268))

Included in the following conference series:

  • 642 Accesses

Abstract

An overview on processor architectures for multimedia applications is presented. Emphasis is on architectural strategies to achieve the required processing power of real-time applications. Architectural approaches for exploitation of the inherent parallelization resources of signal processing schemes are first discussed. The impact of algorithm on the appropriate architectures is displayed for three representative multimedia applications. The discussed applications are block-based video coding as used in MPEG-2, multiplexing for video broadcasing based on OFDM and object oriented video coding according to MPEG-4. Characteristic processor architectures adapted to the needs of these applications are introduced. Architectural structures of the AxPe-DSP, the HiPAR-DSP and a MPEG-4 system are presented as examples. Advances in multimedia processing require processors with high flexibilty on parallel processing and dynamic adaptation capabilties. As promising architectural concepts for advanced multimedia applications reconfigurable computing, simultaneous multithreading, and associative controlling are discussed.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book
USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. M. Berekovic, H.-J. Stolberg, M. B. Kulaczewski and P. Pirsch, “Instruction Set Extension for MPEG-4 Video,” Journal of VLSI Signal Processing 23, pp. 27–49, 1999.

    Article  Google Scholar 

  2. L. Chiariglione, “Impact of MPEG Standards on Multimedia Industry,” Multimedia Signal Processing, Proc. of the IEEE, Vol. 86, No. 6, pp. 1222–1227, June 1998.

    Google Scholar 

  3. J. W. Cooley and J. W. Tukey, “An Algorithm for the Machine Computation of Complex Fourier Series,” Mathematics of Computation, Vol. 9, pp. 297–301, Apr. 1965.

    Google Scholar 

  4. W. Gehrke and K. Gaedke, “Associative Controlling of Monolithic Parallel Processor Architectures,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 5, no. 5, pp. 453–464, Oct. 1995.

    Article  Google Scholar 

  5. S. A. Guccione, “List of FPGA-based Computing Machines,” http://www.io.com/~guccione/HW_list.html, last updated August 21, 2000.

  6. B. Haskell, P. G. Howard, Y. A. Lecun, A. Puri, J. Ostermann, M. R. Civanlar, L. Rabiner, L. Bottou and P. Haffner, “Image andVideo Coding—Emerging Standards and beyond,” IEEE Trans. on Circuits and Systems for Video Technology, Vol. 8 No. 7, pp. 878–891, Nov. 1998.

    Article  Google Scholar 

  7. K. Herrmann, S. Moch, J. Hilgenstock and P. Pirsch, “Implementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit,” Proc. IEEE International Symposium on Defect and FaultTolerance inVLSI Systems (DFT2000), pp. 105–113, Oct. 2000.

    Google Scholar 

  8. ISO/IEC 13818-2, “Generic coding of moving pictures and associated audio, (MPEG-2), Part 2: Video,” Nov. 1993.

    Google Scholar 

  9. ISO/IEC JTC11/SC29/WG11 N2323, “Overview of the MPEG-4 Standard,” July 1998.

    Google Scholar 

  10. ISO/IEC JTC11/SC29/WG11 W2502, “ISO/IEC 14496-2. Final Draft international standard. Part 2: Visual,” Atlantic-City, Oct. 1998

    Google Scholar 

  11. ITU-T Recommendation Draft H.263, “Video Coding for Low Bitrate Communications,” International Telecommunication Union, May 1996.

    Google Scholar 

  12. H. Kloos, L. Friebe, J. P. Wittenburg, W. Hinrichs, H. Lieske and P. Pirsch, “HiPAR-DSP 16, A new DSP for Onboard Real-Time SAR Systems,” Proc. of 15th Aerosense Conference on Phototonic and Quantum Technologies for Aerospace and Application III, July 2001.

    Google Scholar 

  13. J. Kneip, S. Bauer, J. Volmer, B. Schmale, P. Kuhn, M. Reiÿmann, “The MPEG-4 Video Coding Standard—a VLSI point of view,” IEEE InternationalWorkshop on Signal Processing Systems SIPS98, Boston, Oct. 1998.

    Google Scholar 

  14. E. Mirsky, A. DeHon, “MATRIX: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources,” Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pp. 157–166, Apr. 1996.

    Google Scholar 

  15. H. Oehring, U. Sigmund, T. Ungerer, “Simultaneous Multithreading and Multimedia,” Proc. of theWorkshop on Multithreaded Execution, Architecture and Compilation, Orlando, Jan. 1999.

    Google Scholar 

  16. P. Pirsch, “Architectures for Multimedia Signal Processing,” Proc. IEEEWorkshop on Signal Processing Systems, Oct. 1999.

    Google Scholar 

  17. P. Pirsch, J. Kneip, K. Rönner, “Parallelization Resources of Image ProcessingAlgorithms and their Mapping on a Programmable ParallelVideosignal Processor,” Proc. of the International Symposium on Circuits and Systems 1995, pp. I–562–565, Seattle, 1995

    Google Scholar 

  18. B. Radunovic and V. Milutinovic, “A Survey of Reconfigurable Computing Architectures,” 8th International Workshop on Field-Programmable Logic and Applications, pp. 376–385, Tallinn, Estonia, Aug./Sept. 1998.

    Google Scholar 

  19. H. Rohling, R. Grünheid and D. Galda, “OFDM Air Interface for the 4th Generation of Mobile Communication Systems,” Proc. of the 6th International OFDM-Workshop, pp. 1–28, Hamburg, Germany, Sept. 2001.

    Google Scholar 

  20. Russell Tessier and Wayne Burleson, “Reconfigurable Computing for Digital Signal Processing: A Survey,” Journal of VLSI Signal Processing, vol. 28, pp. 7–28, 2001.

    Article  MATH  Google Scholar 

  21. R. M. Tomasulo, “An Efficient Algorithm for Exploiting Multiple Arithmetic Units,” IBM Journal of Research and Development, volume 11(1), pp. 25–33, IBM, 1967

    Article  MATH  Google Scholar 

  22. D. M. Tullsen, S. J. Eggers, H. M. Levy, “Simultaneous Multithreading: Maximizing On-Chip Parallelism,” Proc. of the 22nd Annual International Symposium on Computer Architecture, June 1995.

    Google Scholar 

  23. D. M. Tullsen, J. L. Lo, S. J. Eggers, H. M. Levy, “Supporting Fine-Grain Synchronization on a Simultaneous Multithreaded Processor,” Technical Report #UW-CSE-98-06-02, University of Washington, June 1998.

    Google Scholar 

  24. David W. Wall, “Limits of Instruction-Level Parallelism,” Fourth International Symposium o Architectural Support for Programming Languages and Operating Systems, pp. 176–188, Apr. 1991

    Google Scholar 

  25. J. P. Wittenburg, P. Pirsch, G. Meyer, “A Multithreaded Architecture Approach to Parallel DSPs for High Performance Image Processing Applications,” Proc. of the IEEEWorkshop on Signal Processing Systems, Oct. 1999.

    Google Scholar 

  26. W. Yamamoto, M. J. Serrano, A. R. Talcott, R. C. Wood, M. Nemirovski, “Performance Estimation of Multistreamed, Superscalar Processors,” Proceedings of the 27th Annual Hawaii International Conference on System Sciences, Honolulu, 1994.

    Google Scholar 

Download references

Author information

Authors and Affiliations

  1. Institute of Microelectronic Circuits and Systems, University of Hannover, Hannover

    P. Pirsch, A. Freimann, C. Klar & J. P. Wittenburg

Authors
  1. P. Pirsch
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. A. Freimann
    View author publications

    You can also search for this author in PubMed Google Scholar

  3. C. Klar
    View author publications

    You can also search for this author in PubMed Google Scholar

  4. J. P. Wittenburg
    View author publications

    You can also search for this author in PubMed Google Scholar

Editor information

Editors and Affiliations

  1. Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Niels Bohr Weg 1, 2333, Leiden, CA, The Netherlands

    Ed F. Deprettere

  2. Computer Engineering Laboratory (DATE) Department of Electrical Engineering and Information Technology, University of Paderborn, Warburger Str.100, 33100, Paderborn, Germany

    Jürgen Teich

  3. Computer Engineering Laboratory Electrical Engineering Department, ITS, Delft University of Technology, Mekelweg 4, 2628, CD Delft, The Netherlands

    Stamatis Vassiliadis

Rights and permissions

Reprints and permissions

Copyright information

© 2002 Springer-Verlag Berlin Heidelberg

About this chapter

Cite this chapter

Pirsch, P., Freimann, A., Klar, C., Wittenburg, J.P. (2002). Processor Architectures for Multimedia Applications. In: Deprettere, E.F., Teich, J., Vassiliadis, S. (eds) Embedded Processor Design Challenges. SAMOS 2001. Lecture Notes in Computer Science, vol 2268. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45874-3_11

Download citation

  • DOI: https://doi.org/10.1007/3-540-45874-3_11

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-43322-4

  • Online ISBN: 978-3-540-45874-6

  • eBook Packages: Springer Book Archive

Publish with us

Policies and ethics

Search

Navigation