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A Java-Enabled DSP

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Embedded Processor Design Challenges (SAMOS 2001)

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Abstract

In this paper we explore design techniques and constraints for enabling high-speed Java-enabled wireless devices. Since Java execution may be required for 3G devices, efficient methods of executing Java bytecode are explored. We begin by setting a historical context for DSP architectures and describe salient characteristics of classical, transitional, and modern DSP architectures. We then discuss methods of executing Java bytecode—both software and hardware—and discuss the merits of each approach. We next describe the Delft-Java engine that we designed at Delft Technical University in the Netherlands. Finally, we compare this design to other techniques and comment on ways that Sandbridge Technologies is modifying organizational characteristics to achieve power-efficient Java execution.

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References

  1. J. Eyre and J. Bier. DSP Processors Hit the Mainstream. IEEE Computer, pages 51–59, August 1998.

    Google Scholar 

  2. Junko Yoshida. Java chip vendors set for cellular skirmish. EE Times, January 30 2001.

    Google Scholar 

  3. P. Lapley. DSP Processor Fundamentals. IEEE press, New York, 1997.

    Google Scholar 

  4. M. Saghir, P. Chow, and C. G. Lee. Towards Better DSP Architecture and Compilers. In Proceedings of the International Conference on Signal Processing Applications and Technology, pages 658–664, October 1994.

    Google Scholar 

  5. Texas Instruments. TMS320C54x DSP Reference Set. Volume 1: CPU and Perhipherals. Technical Report SPRU131E, Texas Instruments, June 1998.

    Google Scholar 

  6. Je. Bier. DSP16xxx Targets Communictaions Apps. Microprocessor Report, 11(12), 1997.

    Google Scholar 

  7. G. Ungerboeck, D. Maiwald, H. P. Kaeser, P. R. Chevillat, and J. P. Beraud. Architecture of a Digital Signal Processor. IBM Journal of Research and Development, 29(2), 1985.

    Google Scholar 

  8. N. L. Bernbaum, B. Blaner, D. E. Carmon, J. K. D’Addio, F. E. Grieco, A. M. Jacoutot, M. A. Locker, B. Marshall, D. W. Milton, C. R. Ogilvie, P. M. Schanely, P. C. Stabler, and M. Turcotte. The IBM Mwave 3780i DSP. In Proceedings of the 1996 International Conference on Signal Processing Applications and Technology (ICSPAT’ 96), pages 1287–1291, Boston, MA, October 1996.

    Google Scholar 

  9. Tom R. Halfhill. TI Cores Accelerate DSP Arms Race. Microprocessor Report, March 6 2000.

    Google Scholar 

  10. J. Eyre and J. Bier. Carmel Enables Customizable DSP. Microprocessor Report, 12(17), December 1998.

    Google Scholar 

  11. LSI Corporation. LSI402Z Digital Signal Processor. LSI Corporation, r20012 edition, 1999.

    Google Scholar 

  12. Gerald G. Pechanek, C. John Glossner, William F. Lawless, Daniel H. McCabe, Chris H. L. Moller, and Steven J. Walsh. A Machine Organization and Architecture for Highly Parallel, Scalable, Single Chip DSPs. In Proceedings of the 1995 DSPx Technical Program Conference and Exhibition, pages 42–50, San Jose, California, May 1995.

    Google Scholar 

  13. Gerald G. Pechanek, Mihilo Stojancic, Stamatis Vassiliadis, and C. John Glossner. M.F.A.S.T.: A Single Chip, Highly Parallel Image Processing Architecture. In Proceedings IEEE International Conference on Image Processing, volume I, pages 1375–1379, Arlington, Virginia, October 1995. IEEE Press.

    Google Scholar 

  14. Gerald G. Pechanek, Charles W. Kurak, C. John Glossner, Chris H. L. Moller, and Steven J. Walsh. M.F.A.S.T.: A Highly Parallel Single Chip DSP with a 2D IDCT Example. In Proceeding of the International Conference on Signal Processing Applications and Technology, pages 69–72, Boston, Mass., October 1995.

    Google Scholar 

  15. Gerald G. Pechanek, C. John Glossner, Zhiyong Li, Chris H. L. Moller, and Stamatis Vassiliadis. Tensor Product FFT’s on M.F.A.S.T.: A Highly Parallel Single Chip DSP. In Proceedings of DSP 95—Digital Signal Processing and Its Applications, Paris, France, October 1995.

    Google Scholar 

  16. B. Case. Philips hopes to displace DSPs with VLIW. Microprocessor Report, pages 12–15, December 1997.

    Google Scholar 

  17. C. P. Feigel. TI Introduces Four-Processor DSP Chip. Microprocessor Report, 8(4), March 28 1994.

    Google Scholar 

  18. Dave Epstein. Chromatic Raises the Multimedia Bar. Microprocessor Report, 9(14), October 28 1995.

    Google Scholar 

  19. A. Peleg and U. Weiser. MMX technology extension to the Intel architecture. IEEE Micro, pages 42–50, August 1996.

    Google Scholar 

  20. H. Nguyen and L. K. John. Exploiting SIMD Parallelism in DSP and Multimedia Algorithms Using the AltiVec Technology. In Proceedings of the International Conference on Supercomputing, pages 11–20, 1999.

    Google Scholar 

  21. J. C. Bier, A. Shoham, H. Hakkarainen, O. Wolf, G. Blalock, and Philip D. Lapsley. DSP on General-Purpose Processors: Performance, Architecture, Pitfalls. Berkeley Design Technology, Inc., 1997.

    Google Scholar 

  22. O. Wolf and J. Bier. StarCore Launches First Architecture. Microprocessor Report, 12(14), October 1998.

    Google Scholar 

  23. O. Wolf and J. Bier. TigerSHARC Sinks Teeth Into VLIW. Microprocessor Report, 12(16), December 1998.

    Google Scholar 

  24. J. Fridman and Z. Greenfield. The TigerSHARC DSP Architecture. IEEE Micro, 20(1):66–76, January 2000.

    Article  Google Scholar 

  25. J. Turley and H. Hakkarainen. TI’s New C6x Screams at 1,600 MIPS. Microprocessor Report, 11(2), 1997.

    Google Scholar 

  26. Gerald G. Pechanek, Stamatis Vassiliadis, and Nikos Pitsianis. ManArray processor interconnection network: an introduction. In Euro-Par’ 99 Parallel Processing Proceedings. (Lecture notes in computer science), pages 761–765, Toulouse, France, August/September 1999. Springer, Berlin.

    Google Scholar 

  27. Gerald G. Pechanek and Stamatis Vassiliadis. The ManArray Embedded Processor Architecture. In Proceedings of the 26-th Euromicro Conference: Informatics: inventing the future, volume I, pages 348–355, Maastrict, The Netherlands, September 5–7 2000.

    Google Scholar 

  28. Bryan Ackland and Paul D’Arcy. A New Generation of DSP Architectures. In Proceedings of the 1999 Custom Integrated Circuits Conference, pages 531–536, 1999.

    Google Scholar 

  29. James Gosling, Bill Joy, and Guy Steele, editors. The Java Language Specification. The Java Series. Addison-Wesley, Reading, MA, USA, 1996.

    MATH  Google Scholar 

  30. James Gosling and Henry McGilton. The Java Language Environment: A White Paper. Technical report, Sun Microsystems, Mountain View, California, October 1995. Available from ftp.javasoft.com/docs.

    Google Scholar 

  31. Tim Lindholm and Frank Yellin. The Java Virtual Machine Specification. The Java Series. Addison-Wesley, Reading, MA, USA, 1997.

    Google Scholar 

  32. Cheng-Hsueh A. Hsieh, John C. Gyllenhaal, and Wen mei W. Hwu. Java Bytecode to Native Code Translation: The Caffeine Prototype and Preliminary Results. In Proceeding of the 29th Annual Internation Symposium on Microarchitecture (MICRO-29), pages 90–97, Los Alamitos, CA, USA, December 2–4 1996. IEEE Computer Society Press.

    Google Scholar 

  33. Ali-Reza Adl-Tabatabai, Michal Cierniak, Guie-Yuan Lueh, Vishesh M. Parikh, and James M. Stichnoth. Fast, effective code generation in a just-in-time Java compiler. In Proceeding of the ACM SIGPLAN’ 98 conference on Programming Language Design and Implementation (PLDI’98), volume 33, pages 280–290. Association for Computing Machinery, May 1998.

    Google Scholar 

  34. Gilles Muller, Barbara Moura, Fabrice Bellard, and Charles Consel. JIT vs. Offline Compilers: Limits and Benefits of Bytecode Compilation. Technical Report 1063, IRISA, Campus de Beaulieu, 35042 Rennes Cedex, France, December 1996. http://www.irisa.fr.

    Google Scholar 

  35. Sun Microsystems. The Java Hotspot Performance Engine Architecture. Sun Microsystems, 1999. http://java.sun.com/ products/ hotspot/ whitepaper.html.

  36. Kemal Ebcioglu, Eric R. Altman, and Erdem Hokenek. A Java ILP Machine Based on Fast Dynamic Compilation. In IEEE MASCOTS International Workshop on Security and Efficiency Aspects of Java, Eilat, Israel, January 9–10 1997. IEEE Computer Society Press.

    Google Scholar 

  37. Michal Cierniak and Wei Li. Just-in-time optimizations for high-performance Java programs. Concurrency: Practice and Experience, 9(4):1063–1073, November 1997.

    Article  Google Scholar 

  38. Todd A. Proebsting, Gregg Townsend, Patrick Bridges, John H. Hartman, Tim Newsham, and Scott A. Watterson. Toba: Java For Applications—A Way Ahead of Time (WAT) Compiler. In Proceedings Third Conference on Object-Oriented Technologies and Systems (COOTS’97), 1997.

    Google Scholar 

  39. Hewlett Packard. HP Turbo Chai Release 2.0. Hewlett-Packard, May 1999. http://www.hp.com/emso/products/turbochai/TchaiPDF.pdf.

  40. John Glossner, Jesse Thilo, and Stamatis Vassiliadis. Java Signal Processing: FFT’s with bytecodes. In Proceedings of the 1998 ACM Workshop on Java for High-Performance Network Computing, Stanford University, Palo Alto, California, February 28 and March 1 1998.

    Google Scholar 

  41. John Glossner, Jesse Thilo, and Stamatis Vassiliadis. Java Signal Processing: FFT’s with bytecodes. Journal of Concurrency and Experience, 10(11–13):1173–1178, 1998.

    Article  Google Scholar 

  42. Cygnus. Gcj compiler, 1999.

    Google Scholar 

  43. Sun Microelectronics. picoJava I Microprocessor Core Architecture. Technical Report WPR-0014-01, Sun Microsystems, Mountain View, California, November 1996. Available from http://www.sun.com/ sparc/ whitepapers/ wpr-0014-01.

    Google Scholar 

  44. Marc Tremblay and Micahel O’Connor. picoJava: A Hardware Implementation of the Java Virtual Machine. In Hotchips Presentation, 1996.

    Google Scholar 

  45. Harlan McGhan and Mike O’Connor. PicoJava: A Direct Execution Engine For Java Bytecode. IEEE Computer, 31(10):22–30, October 1998.

    Google Scholar 

  46. L. C. Chang, L. R. Ton, M. F. Kao, and C. P. Chung. Stack operations folding in Java processors. IEE Proceedings—Computers and Digital Techniques, 145(5):333–343, September 1998.

    Google Scholar 

  47. Lee-Ren Ton, Lung-Chung Chang, Min-Fu Kao, Han-Min Tseng, Shi-Sheng Shang, Ruey-Liang Ma, Dze-Chaung Wang, and Chung-Ping Chung. Instruction Folding in Java Processor. In 1997 International Conference on Parallel and Distributed Systems, pages 138–143, Seoul, Korea, December 12–13 1997. IEEE Computer Society Press.

    Google Scholar 

  48. Sun Microelectronics. Sun Microelectronic’s picoJava I Posts Outstanding Performance. Technical Report WPR-0015-01, Sun Microsystems, Mountain View, California, November 1996. Available from http://www.sun.com/ sparc/ whitepapers/wpr-0015-01.

    Google Scholar 

  49. James Gosling. Java Intermediate Bytecodes. In ACM SIGPLAN Notices, pages 111–118, New York, NY, January 1995. Association for Computing Machinery. ACM SIGPLAN Workshop on Intermediate Representations (IR95).

    Google Scholar 

  50. J. Glossner and S. Vassiliadis. Delft-Java Dynamic Translation. In Proceedings of the 25th EUROMICRO conference (EUROMICRO’ 99), volume 1, Milan, Italy, September 8–10 1999.

    Google Scholar 

  51. John Glossner and Stamatis Vassiliadis. Delft-Java Link Translation Buffer. In Proceedings of the 24th EUROMICRO conference, volume 1, pages 221–228, Vasteras, Sweden, August 25–27 1998.

    Google Scholar 

  52. C. John Glossner and Stamatis Vassiliadis. The Delft-Java Engine: An Introduction. In Lecture Notes In Computer Science. Third International Euro-Par Conference (Euro-Par’97 Parallel Processing), pages 766–770, Passau, Germany, Aug. 26–29 1997. Springer-Verlag.

    Google Scholar 

  53. Bil Lewis and Daniel J. Berg. Threads Primer: A Guide to Multithreaded Programming. SunSoft Press—A Prentice Hall Title, Mountain View, California, 1996.

    Google Scholar 

  54. Peter Wayner. Sun gambles on java chips. Byte, 21(11):79–85, November 1996.

    Google Scholar 

  55. S. Vassiliadis, B. Blaner, and R. J. Eickemeyer. SCISM: A Scalable Compound Instruction Set Machine. IBM Journal of Research and Development, 38(1):59–78, January 1994.

    Google Scholar 

  56. James Philips and Stamatis Vassiliadis. High-performance 3-1 interlock collapsing ALU’s. IEEE Transactions on Computers, 43(3):257–268, March 1994.

    Article  Google Scholar 

  57. Brian Case. Implementing the java virtual machine. Microprocessor Report, 10(4):12–17, March 25 1996.

    Google Scholar 

  58. Stamatis Vassiliadis, James Phillips, and Bart Blanar. Interlock Collapsing ALU’s. IEEE Transactions on Computers, 42(7):825–839, July 1993.

    Article  Google Scholar 

  59. R. M. Tomasulo. An Efficient Algorithm for Exploiting Multiple Arithmetic Units. IBM Journal of Research and Development, II:25–33, 1967.

    Article  Google Scholar 

  60. Wes Munsil and Chia-Jiu Wang. Reducing Stack Usage in Java Bytecode Execution. Computer Architecture News, 1(7):7–11, March 1998.

    Article  Google Scholar 

  61. Yamin Li, Sanli Li, Xianzhu Wang, and Wanming Chu. JAViR-Exploiting Instruction Level Parallelism for JAVA Machine by Using Virtual Register. In The Second European IASTED International Conference on Parallel and Distributed Systems, Vienna, Austria, July 1–3 1998.

    Google Scholar 

  62. Advancel Logic Corporation. TinyJ Processor Core Product Datasheet. Datasheet, July 1999.

    Google Scholar 

  63. Patriot Scientific Corporation. Psc1000/a microprocessor datasheet. Patriot Scientific, 1997. http://www.ptsc.com/downloads/ psc1000/specs/datasheet.pdf.

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Author information

Authors and Affiliations

  1. Sandbridge Technologies, Inc., White Plains, NY, USA

    C. John Glossner

  2. Lehigh University, Bethlehem, PA, USA

    Michael Schulte

  3. Delft University of Technology, Delft, The Netherlands

    C. John Glossner & Stamatis Vassiliadis

Authors
  1. C. John Glossner
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  2. Michael Schulte
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  3. Stamatis Vassiliadis
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Editor information

Editors and Affiliations

  1. Leiden Institute of Advanced Computer Science (LIACS), Leiden University, Niels Bohr Weg 1, 2333, Leiden, CA, The Netherlands

    Ed F. Deprettere

  2. Computer Engineering Laboratory (DATE) Department of Electrical Engineering and Information Technology, University of Paderborn, Warburger Str.100, 33100, Paderborn, Germany

    Jürgen Teich

  3. Computer Engineering Laboratory Electrical Engineering Department, ITS, Delft University of Technology, Mekelweg 4, 2628, CD Delft, The Netherlands

    Stamatis Vassiliadis

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© 2002 Springer-Verlag Berlin Heidelberg

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Glossner, C.J., Schulte, M., Vassiliadis, S. (2002). A Java-Enabled DSP. In: Deprettere, E.F., Teich, J., Vassiliadis, S. (eds) Embedded Processor Design Challenges. SAMOS 2001. Lecture Notes in Computer Science, vol 2268. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45874-3_18

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  • DOI: https://doi.org/10.1007/3-540-45874-3_18

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