Abstract
Demands for flexible processing have moved general-purpose processing into the data path of networks. With the development of System-On-a-Chip technology, it is possible to put a number of processors with memory and I/O components on a single ASIC. We present a performance model of such a system and show how the number of processors, cache sizes, and the tradeoffs between the use of on-chip SRAM and DRAM can be optimized in terms of computation per unit chip area for a given workload. Based on a telecommunications benchmark the results of such an optimization are presented and design tradeoffs for Systems-on-a-Chip are identified and discussed.
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© 2002 Springer-Verlag Berlin Heidelberg
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Wolf, T., Franklin, M.A. (2002). Design Tradeoffs for Embedded Network Processors. In: Schmeck, H., Ungerer, T., Wolf, L. (eds) Trends in Network and Pervasive Computing — ARCS 2002. ARCS 2002. Lecture Notes in Computer Science, vol 2299. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45997-9_12
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DOI: https://doi.org/10.1007/3-540-45997-9_12
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